Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: A packing nut assembly for a control valve having a valve body and a valve stem includes a packing box arranged for operative coupling to the valve body and having a primary bore sized to receive the valve stem and first and second counterbores. The first counterbore is sized to receive valve packing and the second counterbore includes internal threads. A packing nut having a central bore is sized to receive the valve stem and includes a threaded outer surface positioned to engage the second counterbore of the packing box. The packing nut includes an adjustment surface positioned to face the first counterbore, and includes an adjustment head having a plurality of tool-receiving apertures sized to receive an adjustment tool.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: A control valve of the ball type with bi-directional shutoff capabilities is disclosed. The ball valve including an inlet and an outlet, a ball element and a seal assembly. When closing the valve, the ball element, which is eccentrically mounted on a shaft, rotates to abut the seal assembly. While closed, the seal assembly including a seal housing, a main seal and a resilient member, contacts the ball element at the main seal, while the resilient member biases the main seal toward the ball element. The seal assembly further includes a secondary flowpath between the main seal and seal housing, which is restricted by a high temperature seal.

Abstract: Universal fluid valve body apparatus and articles of manufacture are disclosed. An example fluid control valve body includes opposing first and second openings and opposing third and fourth openings. Each of the third and fourth openings is disposed at a respective angle to at least one of the first and second openings and one of the third and fourth openings is configured to enable the fluid control valve body to be mounted directly to a vessel.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1?yGey, within a relaxed Si1?xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.

Abstract: A control valve having a seat ring assembly constructed from a unitary piece of material is disclosed. The seat ring assembly may include a base which serves as a valve seat for the valve plug of the valve, and which includes a plurality of exterior threads adapted to rotatably attach to a plurality of interior threads provided within the valve body. The seat ring assembly may also include a post-guided bearing surface to maintain alignment of the valve plug to the valve seat. The seat ring assembly can be secured to the valve body simply by threadably attaching the elements. Moreover, by providing the valve seat and the guide surface as integral parts of the seat ring assembly, manufacturing costs and maintenance requirements are reduced and subsequent seal leak performance is increased.

Abstract: A control valve of the ball type with bi-directional shutoff capabilities is disclosed. The ball valve including an inlet and an outlet, a ball element and a seal assembly. When closing the valve, the ball element, which is eccentrically mounted on a shaft, rotates to abut the seal assembly. While closed, the seal assembly including a seal housing, a main seal and a resilient member, contacts the ball element at the main seal, while the resilient member biases the main seal toward the ball element. The seal assembly further includes a secondary flowpath between the main seal and seal housing, which is restricted by two unidirectional seal rings.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: A wall system, head joint drainage device and method adapted to allow drainage of moisture from a head joint of a structure meeting a horizontal interruption when the wall system is formed with a plurality of building products set with mortar forming a mortar joint between adjacent ones of the plurality of modular building products. A spacer has a top portion, having a length approximately equal to a depth of the plurality of building products and a width approximately equal to a width of the mortar joint, adapted to block the mortar from reaching the horizontal interruption and has a side portion adapted to keep the portion a distance away from the horizontal interruption, the distance allowing moisture drainage from the head joint.

Abstract: A device for use in structures having masonry cavity wall construction for promoting removal of water and water vapor between a masonry exterior wall and a structural back-up wall. A plurality of the devices, which are elongated and have a generally “V” shape, are arranged in a systematic pattern in order to catch and retain trash mortar during a construction phase of the structure. Following construction, the device, which includes a wicking material to transport accumulated water beyond ends of the device, functions to promote the removal of water and water vapor in the cavity so as to prevent deterioration of the building materials of the walls.

Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1-yGey, within a relaxed Si1-xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.