Patents by Inventor John L. Kelley
John L. Kelley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957893Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.Type: GrantFiled: August 25, 2020Date of Patent: April 16, 2024Assignee: Medtronic, Inc.Inventors: Brad C. Tischendorf, John E. Kast, Thomas P. Miltich, Gordon O. Munns, Randy S. Roles, Craig L. Schmidt, Joseph J. Viavattine, Christian S. Nielsen, Prabhakar A. Tamirisa, Anthony M. Chasensky, Markus W. Reiterer, Chris J. Paidosh, Reginald D. Robinson, Bernard Q. Li, Erik R. Scott, Phillip C. Falkner, Xuan K. Wei, Eric H. Bonde, David A. Dinsmoor, Duane L. Bourget, Forrest C M Pape, Gabriela C. Molnar, Joel A. Anderson, Michael J. Ebert, Richard T. Stone, Shawn C. Kelley, Stephen J. Roddy, Timothy J. Denison, Todd V. Smith
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Patent number: 11957894Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.Type: GrantFiled: August 25, 2020Date of Patent: April 16, 2024Assignee: Medtronic, Inc.Inventors: Anthony M. Chasensky, Bernard Q. Li, Brad C. Tischendorf, Chris J. Paidosh, Christian S. Nielsen, Craig L. Schmidt, David A. Dinsmoor, Duane L. Bourget, Eric H. Bonde, Erik R. Scott, Forrest C M Pape, Gabriela C. Molnar, Gordon O. Munns, Joel A. Anderson, John E. Kast, Joseph J. Viavattine, Markus W. Reiterer, Michael J. Ebert, Phillip C. Falkner, Prabhakar A. Tamirisa, Randy S. Roles, Reginald D. Robinson, Richard T. Stone, Shawn C. Kelley, Stephen J. Roddy, Thomas P. Miltich, Timothy J. Denison, Todd V. Smith, Xuan K. Wei
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Patent number: 8024393Abstract: Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.Type: GrantFiled: December 3, 2007Date of Patent: September 20, 2011Assignee: MIPS Technologies, Inc.Inventors: Ying-wai Ho, John L. Kelley, XingYu Jiang
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Patent number: 7707389Abstract: A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction staging unit dispatches the expand instruction to a first recoder and the expandable instruction to a second recoder of a recoding unit. At least one information bit based on the expand instruction is generated at the first recoder. The second recoder uses the at least one information bit generated at the first recoder to recode the expandable instruction, and the recoded expandable instruction is placed in an instruction buffer.Type: GrantFiled: October 31, 2003Date of Patent: April 27, 2010Assignee: MIPS Technologies, Inc.Inventors: Soumya Banerjee, John L. Kelley, Ryan C. Kinter
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Publication number: 20080183791Abstract: Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.Type: ApplicationFiled: December 3, 2007Publication date: July 31, 2008Applicant: MIPS Technologies, Inc.Inventors: Ying-wai Ho, John L. Kelley, XingYu Jiang
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Patent number: 7346643Abstract: Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.Type: GrantFiled: July 30, 1999Date of Patent: March 18, 2008Assignee: MIPS Technologies, Inc.Inventors: Ying-wai Ho, John L. Kelley, XingYu Jiang
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Patent number: 6912559Abstract: The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate result (IR1) according to the equation: IR1=1?N*Xi; (c) multiplying IR1 by Xi to produce a second intermediate result (IR2); and (d) adding Xi to IR2 to produce an approximation of the reciprocal of N. Approximating the reciprocal square root includes: (a) estimating the reciprocal square root of N to produce Xi; (b) multiplying Xi by N to produce IR1; (c) determining IR2 according to the equation: IR2=(1?Xi*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number.Type: GrantFiled: July 30, 1999Date of Patent: June 28, 2005Assignee: MIPS Technologies, Inc.Inventors: Ying-wai Ho, Michael J. Schulte, John L. Kelley
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Patent number: 6631392Abstract: A method and apparatus predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point operation. Predictions are made based on at least one overflow threshold value, at least first and second underflow threshold values, and a preliminary result exponent value derived from the values of the exponents of the floating-point numbers that are about to be acted upon. The preliminary result exponent is compared to an overflow or underflow threshold value in order to predict whether there is a possibility that an overflow or underflow floating-point exception could occur. Overflow and underflow exceptions are predicted and an exception prediction signal is generated. The exception prediction signals that are generated may be used by data processing system control units, for example, to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception.Type: GrantFiled: July 30, 1999Date of Patent: October 7, 2003Assignee: MIPS Technologies, Inc.Inventors: XingYu Jiang, Ying-wai Ho, John L. Kelley
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Publication number: 20020116431Abstract: The invention provides a system and method for improving the accuracy of approximating the reciprocal of a number and the reciprocal square root of a number. A method according to the present invention for approximating the reciprocal square root of a number (N) includes the steps of: (a) estimating the reciprocal square root of the number to produce an estimate (Xi); (b) multiplying Xi by N to produce a first intermediate result (IR1); (c) determining a second intermediate result (IR2) according to the equation: IR2=(1−Xi,*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number. This method provides one advantage because of the order in which the multiplication is performed makes it likely that all results will be in normalized form. Specifically, the Newton-Raphson algorithm requires one to determine the product of: N*Xi*Xi.Type: ApplicationFiled: January 25, 2002Publication date: August 22, 2002Inventors: Ying-wai Ho, Michael J. Schulte, John L. Kelley
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Patent number: 4569446Abstract: This relates to a method of and an apparatus for feeding a product which includes fines to a weigh hopper. In lieu of the usual feeder pan, the last feeder pan in the feeder system is a duplex feeder pan including an upper feeding pan or level and a lower feeding pan or level. The upper feeder pan is provided with selected apertures therein so that fines will be separated from the remainder of the product and directed into the lower feeder pan. During the normal filling of the weigh hopper, both the upper feeder pan and the lower feeder pan will discharge into the weigh hopper. When a pre-selected underweight condition occurs, at least a part of the product from the upper pan will be diverted from immediately entering into the weigh hopper, while the feeding of the fines will continue so as to bring the weight of the product within the weigh hopper up to the pre-selected weight with a minimum of overweight.Type: GrantFiled: October 29, 1982Date of Patent: February 11, 1986Assignee: Kelley-Perry, IncorporatedInventor: John L. Kelley