Abstract: An adapter is connected between a peripheral controller and an intelligent peripheral device. The adapter allows the peripheral device to communicate with the controller. The adapter has control logic rather than a microprocessor for transmitting and receiving data. The control logic is comprised of combinatorial logic circuitry and a command register. The command register allows the controller to configure the cominatorial logic circuitry in order to control adapter operation.

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.