Abstract: In certain embodiments, compensating for misalignment comprises receiving, at a detector array, electromagnetic (E-M) radiation from a target object. The detector array comprises time delay and integration (TDI) detectors organized into segments. Each segment comprises one or more rows of detectors perpendicular to a designed scan axis, and comprises columns of detectors parallel to the designed scan axis. The detector array moves in a relative scan direction relative to the target object. The following is performed for each segment and for each column of each segment. If there is misalignment at a segment, a signal is passed to a correcting next column of a next segment in the direction of the misalignment, where the signal accumulates scan data of a portion of the target object. Otherwise, the signal is passed to a designed next column of the next segment in the direction of the designed scan axis.

Abstract: A charge injection circuit is used to control injection of an electronic charge to be added to a photon-induced charge generated by a detector of a direct integration circuit. The electronic charge can be injected directly to the detector or through a parallel path to the detector.

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal.

Abstract: In certain embodiments, an imaging device includes an image sensor that includes a detector array. The detector array includes a plurality of detectors operable to receive a charge generated by light. The detector array also includes a plurality of detector sub-arrays each including one or more of the plurality of detectors. The one or more detectors of each detector sub-array are in a time delay and integration (TDI) configuration. The image sensor of the imaging device is operable to, for each of the plurality of detector sub-arrays of the detector array, generate an image signal corresponding to a scan of an object.

Abstract: In certain embodiments, a system is provided for image capture that includes a unit cell that includes a Capacitor TransImpedance Amplifier (CTIA) subcircuit, a Source Follower per Detector (SFD) subcircuit, and a Direct Injection (DI) subcircuit. The unit cell may operate using one of the subcircuits selected in response to a control signal. A column amplifier may be coupled to the unit cell. The column amplifier may be operable to receive an intermediate signal from the unit cell and couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal. The column amplifier may generate an output signal from the intermediate signal using the coupled components of the column amplifier.

Abstract: A unit cell includes a MOSFET and an integration capacitor. The MOSFET includes a source, a drain, and a gate. The drain is coupled to the source, and the MOSFET is operable to store a first portion of an electric charge corresponding to a detected light intensity. The integration capacitor includes a first end and a second end. The first end is coupled to the drain of the MOSFET and the second end is coupled to a ground. The integration capacitor is operable to store a second portion of the electric charge corresponding to the detected light intensity.

Abstract: In certain embodiments, a unit cell is provided. The unit cell may include a high sensitivity path and a low sensitivity path. The high sensitivity path may include a first transistor and a first switch. The first switch may couple an output node to the first transistor. The low sensitivity path may include a capacitor. A second switch may couple the high sensitivity path to the low sensitivity path. A third switch may couple the high sensitivity path and the low sensitivity path to a voltage node.

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal.

Abstract: A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges.

Abstract: A time delay integration circuit in which a number of unit cell inputs (101, 103, 105, 107) along with their respective switches (170, 171, 172, 173) are input to a bi-directional BBD circuit (110). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs (111, 112; 113, 114; 115, 116; 117, 118; 119, 120; 121, 122; 123, 124; 125, 126; 127, 128; 129, 130; 131, 132; 133, 134; 135, 136; 137, 138; 139, 140; 141, 142) connected in series and numerous storage capacitors (151, 152,153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases Ø1 and Ø2.

Abstract: An electronic circuit device for driving a load comprises a load terminal, a control terminal and a power terminal for connection to a source of electric power. The load terminal may be in an emitter or a source circuit of the circuit device, and connects to a power supply return terminal by means of three electric elements connected in parallel, namely, the capacitance of a load, a bias current supply, and a current bypass. A voltage sensor is connected between the control terminal and the load terminal for sensing a voltage drop developed between the control terminal and the load terminal. The voltage sensor it is operative to activate the bypass to conduct current in parallel with current flow of the current source in the situation wherein the voltage drop exceeds a threshold. Thereby, the circuit device drives the load in one direction, and the current source and the bypass drive the load in the opposite correction.

Abstract: An amplifier circuit, referred to as a charge mode capacitor transimpedance amplifier (or CM-CTIA) an input node (IN) and an output node (OUT), and includes a transistor (M.sub.IN) having a gate terminal (G) coupled to the input node, a source terminal (S), and a drain terminal (D) coupled to the output node, a first capacitance (C.sub.FB) coupled between the gate terminal and the drain terminal, a second capacitance (C.sub.S) coupled between the source terminal and a first potential (GND), a third capacitance (C.sub.D) coupled between the drain terminal and the first potential or another fixed potential, a first switch (SW1) coupled between a second potential and the drain terminal, and a second switch (SW2) coupled between a third potential (V.sub.RESET) and the gate terminal. During use, the input node is coupled to an output of a radiation detector, such as a photovoltaic IR detector (12) that forms one element or pixel of an array of IR detectors.

Abstract: An array (10) of photoconductive (PC) radiation detectors includes a substrate (1) and a body (12) of PC material that is disposed upon the substrate. The body of PC material has a substantially linear shape. A plurality of electrical interconnects (14, 15) are electrically coupled to the body of PC material for differentiating the body into a plurality of radiation detector sites, individual ones of the plurality of radiation detector sites being disposed in a serial arrangement with one another along a length of the body of PC material. The array further includes a bias current input terminal (16) that is electrically coupled to a first end of the body of PC material and a bias current output terminal (18) that is electrically coupled to a second end of the body of PC material. As a result, a bias current that is applied to the bias current input terminal, and that is extracted from the bias current output terminal, flows through each of the plurality of serially disposed radiation detector sites.

Abstract: All of the resistors in a magnetic field sensitive circuit, both magnetoresistors (MRs) and fixed resistors (FRs), are formed simultaneously in a common fabrication process from a common magentoresistive material. An additional structure in the form of Hall shorting strips is applied to selected resistors to rendered them MRs, while the resistors without the additional structure function as FRs. In one circuit the resistors are arranged in pairs in two voltage divider circuits. The high voltage resistor for one circuit and the low voltage resistor from the other circuit are MRs while the remaining resistors are FRs, producing an increased magnetic sensitivity. In another circuit all resistors are MRs and are positioned so that the magentic field at one pair swings in a direction opposite to that of the other pair, further increasing the magnetic sensitivity. Discrepancies stemming from temperature coefficient mismatch and manufacturing variations are substantially reduced.