Abstract: A magnetic read/write head is produced with an insert layer between the substrate and the magnetic transducer. The insert layer has a lower coefficient of thermal expansion than the substrate, which reduces the temperature pole tip recession (T-PTR) of the head because the insert layer is an intervening layer between the substrate and magnetic transducer. The insert layer is produced by plating, e.g., an Invar layer over the substrate prior to fabricating the magnetic transducer. The Invar layer is annealed and the structure planarized prior to depositing a non-magnetic gap layer followed by the fabrication of the magnetic transducer.

Abstract: The present invention provides an electrodeposition/plating method for metal films and alloys in a bath which contain ferric ions and which usually deposit with high stress, but which when electrodeposited under pulse plating conditions in the presence of low valence vanadium or other ions capable of existing in multiple valence states produce low stress films and alloys and furthermore when plated through a mask creep laterally through walls and creep laterally along the surface of the mask to permit formation of overhangers, bridges, heat exchangers, and other complex three dimensional micro structures of low stress.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.

Abstract: An electroplated film is deposited over a substrate with a plating frame pattern that includes a plating field defined by a plurality of individual features. By dividing the plating field into a plurality of individual features, the delamination force at any location on the plating field is greatly reduced. Thus, a film with a large stress, such as a high moment film, may be plated to a greater thickness than is possible with conventionally plated films.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: A universal interface for communicating information to a proprietary physical interface. At least one output module is provided for transmitting information and an input module is provided for receiving the information. The output module and the input module are configured according to communication parameters of a predetermined type of physical interface to which the output module and the input module interface such that communication of the information is facilitated therebetween.

Abstract: A protocol and header format of a network architecture for communication between a plurality of network devices. In particular, the data frame is resolved at the source device to ascertain the data frame type, and the data frame is forwarded with a virtual network identifier and priority information from the source device to a destination device of the network. The forwarded data frame also includes control information.

Abstract: A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.

Abstract: A cell scheduling method and apparatus are described in which cells are efficiently scheduled in four steps. In a first step, a VC is selected for servicing and serviced if necessary. In a second step, cells from the serviced VCs are scheduled for transmission. In a third step, jitter is controlled. In a fourth step, final departure of cells is scheduled.

Abstract: An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors.

Abstract: A toy flashlight formed in a configuration including a strobe module. The flashlight includes a handle housing and a releasably mounted transparent enclosure with the strobe module enclosed therebetween. The strobe module is provided to switch a light source between ON state and an OFF state to create a rapidly blinking light. Further, a strobing circuit is provided to control the switching mechanism of the strobe module. In this manner, the strobe module with strobing circuit can be inserted into a conventional flashlight to enhance its play value.