Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

Abstract: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

Abstract: An anti-tampering device and method to inhibit or prevent unauthorized probing of an electronic circuit. Propriety target circuitry transmits a distinct signature in the form of an RF signal which is received by the RF anti-tampering detection circuitry. The transmitted RF signature is monitored by the RF anti-tampering detection circuitry for user-defined changes. In the event an unauthorized attempt is made to probe the target system electronics, the mass of the probe alters the RF transmission characteristics of the RF transmission media, changing the RF signature. The altered RF signature is received by the receiving antenna and RF receiver and is processed by signal processing electronics. The change in the RF signature indicates a tamper event and a predefined anti-tamper event is generated.

Abstract: A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: Methods of screening for ligands of the GPR40 receptor are provided, including methods utilizing fatty acid GPR40 ligands.

Abstract: Method and system to centrally monitor the quality of images of financial documents. Embodiments of the present invention can provide a way to monitor and evaluate the quality of images of financial documents stored for remote access by financial institutions. In some embodiments, a standard quality analysis of at least some of the images is performed, and, based on the quality analysis, suspect images are identified to a responsible entity. For at least some of the images, a decisioning result from the responsible entity is recorded in association with information identifying the images. The quality analysis can be applied based on exclusion criteria such as an amount threshold, certain routing information, etc. The suspect images can be identified by sending a quality results file to the responsible entity, and a decisioning result can be received in a decisioning results file.

Abstract: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: Methods of screening for ligands of the GPR40 receptor are provided, including methods utilizing fatty acid GPR40 ligands.

Abstract: In a braiding machine having a braiding assembly which comprises a plurality of yarn carriers moving about a bed to interlace the yarns to form a braided fabric, a take-up including take-off rolls engaging and drawing off the just braided fabric, and a drive for driving the braiding assembly about the bed and the take-off rolls of the take-up. The drive comprises a drive train connecting the braiding assembly and the take-up with a power source. The drive train includes a first mechanical variator, having a control knob, interposed between the braiding assembly and the power source for driving the yarn carriers about the bed, and a second variator, having control knob, connected with the power source for driving the take-off rolls of the take-up. The variators are operative to adjust the rate of rotation of the yarn carriers about the bed and the rate of rotation of the take-off rolls of the take-up to achieve a desired product at maximum machine efficiency.

Abstract: A method and system for monitoring process parameters associated with a manufacturing or testing process. The system includes: at least one machine which is used in the manufacturing or testing process; at least one sensing device, coupled to the at least one machine, for measuring a process parameter associated with the at least one machine; and a controller, coupled to the at least one sensing device, for receiving and storing measured data from the at least one sensing device. The method includes the acts of: measuring a value of a process parameter associated with a machine used in the manufacturing or testing process; converting the measured value of the process parameter into a digital data signal having a specified data format; transmitting the digital data signal to a controller; and storing the digital data signal in a database.

Abstract: A braiding machine with components comprising a support table mounting a plurality of individual segments forming a bed having a substantially circular tracking groove. Each segment comprises a segment groove which comprises a pair of opposed transfer openings formed through the outer wall with the transfer openings of adjacent segments being in contact forming the tracking groove as an endless ring. The size of the endless ring is determined by the number and size of the segments used. The tracking groove may be coated with a selected material other than the material forming the segment.

Abstract: In a braiding machine having a braiding assembly which comprises a plurality of yarn carriers moving about a bed to interlace the yarns to form a braided fabric, a take-up including take-off rolls engaging and drawing off the just braided fabric, and a drive for driving the braiding assembly about the bed and the take-off rolls of the take-up. The drive comprises a drive train connecting the braiding assembly and the take-up with a power source. The drive train includes a first mechanical variator, having a control knob, interposed between the braiding assembly and the power source for driving the yarn carriers about the bed, and a second variator, having control knob, connected with the power source for driving the take-off rolls of the take-up. The variators are operative to adjust the rate of rotation of the yarn carriers about the bed and the rate of rotation of the take-off rolls of the take-up to achieve a desired product at maximum machine efficiency.

Abstract: Apparatus and method for accommodating and handling excess deliveries of combined sewage overflows to a sewage treatment plant supported and contained within an offshore moored vessel or platform, by diverting the excess deliveries to ballast tanks for temporary displacement of clean ballast water and to be returned to the treatment system when excess deliveries of combined sewage overflow are relieved. Fluids contained within the ballast tanks are utilized to provide buoyant support for process tankage. Baffles within the ballast tanks minimize undesirable mixing of the combined sewage overflows with the resident clean ballast water.

Abstract: An alignment device for use in welding which includes a saddle style support which rests upon a first pipe. A second pipe is clamped to the saddle style support in an orientation substantially perpendicular to the first pipe upon which the saddle style support rests. The second pipe serves as a carrier member of a fitting, such as a weldolet. Cinch straps can be used with the saddle style support to facilitate welding on the underside of horizontal pipes or on vertical pipes.