Patents by Inventor John M. Bedinger
John M. Bedinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11363722Abstract: A low permeability laminate film includes one or more low moisture permeability homogeneous polymer films with a total thickness between 0.5 and ten mils without glass or ceramic fillers and with a moisture permeability measured at 37° C. and 100% RH of less than 2.6 E-05 atm·cc·mm/in2·sec of air. The polymer film includes one of polychlorotrifluoroethylene, polytetrafluorethylene, fluorinated ethylene propylene, and perfluoro alkoxy alkane. The low permeability laminate film further includes a nanolaminate including alternate combinations of nanolaminate material that is selected from the group consisting of alumina, titanium dioxide, zirconium oxide, beryllium oxide, hafnium oxide, titanium oxide, silicon nitride, tantalum nitride, silica, parylene F, parylene AF-4, parylene HT® and PTFE (polytetrafluoroethylene). A resulting coated nanolaminate film has a moisture permeability less than an equivalent standard leak rate per square inch of 3.0 E-08 atm·cc/in2·sec of air.Type: GrantFiled: November 9, 2020Date of Patent: June 14, 2022Assignee: RAYTHEON COMPANYInventor: John M. Bedinger
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Publication number: 20210100107Abstract: A low permeability laminate film includes one or more low moisture permeability homogeneous polymer films with a total thickness between 0.5 and ten mils without glass or ceramic fillers and with a moisture permeability measured at 37° C. and 100% RH of less than 2.6 E-05 atm·cc·mm/in2·sec of air. The polymer film includes one of polychlorotrifluoroethylene, polytetrafluorethylene, fluorinated ethylene propylene, and perfluoro alkoxy alkane. The low permeability laminate film further includes a nanolaminate including alternate combinations of nanolaminate material that is selected from the group consisting of alumina, titanium dioxide, zirconium oxide, beryllium oxide, hafnium oxide, titanium oxide, silicon nitride, tantalum nitride, silica, parylene F, parylene AF-4, parylene HT® and PTFE (polytetrafluoroethylene). A resulting coated nanolaminate film has a moisture permeability less than an equivalent standard leak rate per square inch of 3.0 E-08 atm·cc/in2·sec of air.Type: ApplicationFiled: November 9, 2020Publication date: April 1, 2021Inventor: John M. Bedinger
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Publication number: 20200359506Abstract: A low permeability laminate film includes one or more low moisture permeability homogeneous polymer films with a total thickness between 0.5 and ten mils without glass or ceramic fillers and with a moisture permeability measured at 37° C. and 100% RH of less than 2.6 E-05 atm·cc·mm/in2·sec of air. The polymer film includes one of polychlorotrifluoroethylene, polytetrafluorethylene, fluorinated ethylene propylene, and perfluoro alkoxy alkane. The low permeability laminate film further includes a nanolaminate including alternate combinations of nanolaminate material that is selected from the group consisting of alumina, titanium dioxide, zirconium oxide, beryllium oxide, hafnium oxide, titanium oxide, silicon nitride, tantalum nitride, silica, parylene F, parylene AF-4, parylene HT® and PTFE (polytetrafluoroethylene). A resulting coated nanolaminate film has a moisture permeability less than an equivalent standard leak rate per square inch of 3.0 E-08 atm·cc/in2·sec of air.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventor: John M. Bedinger
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Patent number: 10834825Abstract: A low permeability laminate film includes one or more low moisture permeability homogeneous polymer films with a total thickness between 0.5 and ten mils without glass or ceramic fillers and with a moisture permeability measured at 37° C. and 100% RH of less than 2.6 E-05 atm·cc·mm/in2·sec of air. The polymer film includes one of polychlorotrifluoroethylene, polytetrafluorethylene, fluorinated ethylene propylene, and perfluoro alkoxy alkane. The low permeability laminate film further includes a nanolaminate including alternate combinations of nanolaminate material that is selected from the group consisting of alumina, titanium dioxide, zirconium oxide, beryllium oxide, hafnium oxide, titanium oxide, silicon nitride, tantalum nitride, silica, parylene F, parylene AF-4, parylene HT® and PTFE (polytetrafluoroethylene). A resulting coated nanolaminate film has a moisture permeability less than an equivalent standard leak rate per square inch of 3.0 E-08 atm·cc/in2·sec of air.Type: GrantFiled: May 8, 2019Date of Patent: November 10, 2020Assignee: RAYTHEON COMPANYInventor: John M. Bedinger
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Patent number: 9899717Abstract: A stacked stripline circulator includes a first ferrite disc, a second ferrite disc, a first substrate having a metalized edge with the first ferrite disc disposed in the first substrate, a second substrate having a metalized edge with the second ferrite disc disposed in the second substrate, a first metalized pattern defining ports of a circulator disposed on the first substrate, the first metalized pattern comprising copper, a second metalized pattern defining ports of a circulator disposed on the second substrate, the second metalized pattern comprising copper, and a bonding ring bonding the metalized edge of the first substrate with the metalized edge of the second substrate.Type: GrantFiled: October 13, 2015Date of Patent: February 20, 2018Assignee: RAYTHEON COMPANYInventors: John M. Bedinger, Sankerlingam Rajendran
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Publication number: 20170104256Abstract: A stacked stripling circulator includes a first ferrite disc, a second ferrite disc, a first substrate having a metalized edge with the first ferrite disc disposed in the first substrate, a second substrate having a metalized edge with the second ferrite disc disposed in the second substrate, a first metalized pattern defining ports of a circulator disposed on the first substrata, the first metalized pattern comprising copper, a second metalized pattern defining ports of a circulator disposed on the second substrate, the second metalized pattern comprising copper, and a bonding ring bonding the metalized edge of the first substrate with the metalized edge of the second substrate.Type: ApplicationFiled: October 13, 2015Publication date: April 13, 2017Applicant: RAYTHEON COMPANYInventors: John M. Bedinger, Sankerlingam Rajendran
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Patent number: 8857050Abstract: A method includes providing a circuit board having an outer surface, the outer surface configured with a plurality of discrete electrical components that are each manufactured independently of one another, and coating the outer surface and the plurality of discrete electrical components with a first protective dielectric layer. The method further includes coating the first protective dielectric layer with a second dielectric layer. The second dielectric layer includes a dielectric material having a modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 2.7, a dielectric loss less than 0.002, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, a defect densities less than 0.5/centimeter, a pinhole free in films greater than 50 Angstroms, and is capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.Type: GrantFiled: July 31, 2009Date of Patent: October 14, 2014Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Patent number: 8319112Abstract: A circuit board assembly includes a circuit board having an outer surface, the outer surface being configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a domed lid enclosure disposed over one of the plurality of discrete electrical components and an additional dielectric coating overlying the outer surface and the domed lid enclosure.Type: GrantFiled: July 31, 2009Date of Patent: November 27, 2012Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Patent number: 8173906Abstract: According to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The first protective dielectric layer overlays the circuit assembly. The second dielectric layer overlays the first protective dielectric layer and is made of a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), dielectric constant less than 2.7, dielectric loss less than 0.008, breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), temperature stability to 300° Celsius, defect densities less than 0.5/centimeter, pinhole free in films greater than 50 Angstroms, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.Type: GrantFiled: August 31, 2007Date of Patent: May 8, 2012Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Patent number: 8148830Abstract: A circuit board assembly includes a circuit board having an outer surface configured with a plurality of discrete electrical components. The assembly includes a first protective dielectric layer overlying the outer surface, and a second dielectric layer overlying the first protective dielectric layer and the discrete electrical components. The second dielectric layer includes a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 3.0, a dielectric loss less than 0.008, a moisture absorption less than 0.04 percent, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 300° Celsius, pinhole free in films greater than 50 Angstroms, hydrophobic with a wetting angle greater than 45 degrees, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.Type: GrantFiled: July 31, 2009Date of Patent: April 3, 2012Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Patent number: 7902083Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.Type: GrantFiled: January 21, 2010Date of Patent: March 8, 2011Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
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Patent number: 7767589Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.Type: GrantFiled: August 31, 2007Date of Patent: August 3, 2010Assignee: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
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Publication number: 20100120254Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.Type: ApplicationFiled: January 21, 2010Publication date: May 13, 2010Applicant: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
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Publication number: 20090288876Abstract: A circuit board assembly includes a circuit board having an outer surface that is configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a first protective dielectric layer overlying the outer surface, and a second dielectric layer overlying the first protective dielectric layer and the discrete electrical components. The second dielectric layer includes a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 3.0, a dielectric loss less than 0.008, a moisture absorption less than 0.04 percent, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 300° Celsius, pinhole free in films greater than 50 Angstroms, hydrophobic with a wetting angle greater than 45 degrees, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.Type: ApplicationFiled: July 31, 2009Publication date: November 26, 2009Applicant: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Publication number: 20090290314Abstract: A circuit board assembly includes a circuit board having an outer surface, the outer surface being configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a domed lid enclosure disposed over one of the plurality of discrete electrical components and an additional dielectric coating overlying the outer surface and the domed lid enclosure.Type: ApplicationFiled: July 31, 2009Publication date: November 26, 2009Applicant: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Publication number: 20090291200Abstract: A method includes providing a circuit board having an outer surface, the outer surface configured with a plurality of discrete electrical components that are each manufactured independently of one another, and coating the outer surface and the plurality of discrete electrical components with a first protective dielectric layer. The method further includes coating the first protective dielectric layer with a second dielectric layer. The second dielectric layer includes a dielectric material having a modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 2.7, a dielectric loss less than 0.002, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, a defect densities less than 0.5/centimeter, a pinhole free in films greater than 50 Angstroms, and is capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.Type: ApplicationFiled: July 31, 2009Publication date: November 26, 2009Applicant: Raytheon CompanyInventors: John M. Bedinger, Michael A. Moore
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Publication number: 20080185174Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.Type: ApplicationFiled: August 31, 2007Publication date: August 7, 2008Inventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
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Publication number: 20080185173Abstract: According to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The first protective dielectric layer overlays the circuit assembly. The second dielectric layer overlays the first protective dielectric layer and is made of a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), dielectric constant less than 2.7, dielectric loss less than 0.008, breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), temperature stability to 3000 Celsius, defect densities less than 0.5/centimeter, pinhole free in films greater than 50 Angstroms, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.Type: ApplicationFiled: August 31, 2007Publication date: August 7, 2008Inventors: John M. Bedinger, Michael A. Moore
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Patent number: 6958260Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.Type: GrantFiled: August 19, 2003Date of Patent: October 25, 2005Assignee: Texas Instruments IncorporatedInventors: John M. Bedinger, Clyde R. Fuller
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Publication number: 20040036168Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.Type: ApplicationFiled: August 19, 2003Publication date: February 26, 2004Inventors: John M. Bedinger, Clyde R. Fuller