Patents by Inventor John M. Birkner
John M. Birkner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6150199Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.Type: GrantFiled: September 27, 1999Date of Patent: November 21, 2000Assignee: QuickLogic CorporationInventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
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Patent number: 6078191Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: March 10, 1998Date of Patent: June 20, 2000Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5989943Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.Type: GrantFiled: December 8, 1989Date of Patent: November 23, 1999Assignee: QuickLogic CorporationInventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
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Patent number: 5986468Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: December 11, 1997Date of Patent: November 16, 1999Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5780919Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.Type: GrantFiled: May 21, 1996Date of Patent: July 14, 1998Assignee: QuickLogic CorporationInventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
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Patent number: 5726586Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: November 5, 1996Date of Patent: March 10, 1998Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5717230Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.Type: GrantFiled: October 13, 1994Date of Patent: February 10, 1998Assignee: QuickLogic CorporationInventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
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Patent number: 5594364Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: June 23, 1995Date of Patent: January 14, 1997Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5587669Abstract: In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.Type: GrantFiled: March 3, 1995Date of Patent: December 24, 1996Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua T. Chua
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Patent number: 5502315Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.Type: GrantFiled: December 2, 1993Date of Patent: March 26, 1996Assignee: QuickLogic CorporationInventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
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Patent number: 5430390Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: May 17, 1994Date of Patent: July 4, 1995Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5416367Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.Type: GrantFiled: January 31, 1994Date of Patent: May 16, 1995Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua T. Chua, William D. Cox
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Patent number: 5293133Abstract: A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device.Type: GrantFiled: August 27, 1992Date of Patent: March 8, 1994Assignee: QuickLogic CorporationInventors: John M. Birkner, David T. Martin, Richard J. Wong
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Patent number: 5280202Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: March 2, 1993Date of Patent: January 18, 1994Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 5122685Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.Type: GrantFiled: March 6, 1991Date of Patent: June 16, 1992Assignee: QuickLogic CorporationInventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
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Patent number: 4933577Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.Type: GrantFiled: April 10, 1989Date of Patent: June 12, 1990Assignee: Advanced Micro Devices, Inc.Inventors: Sing Y. Wong, John M. Birkner
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Patent number: 4862136Abstract: A programmable resistor network and a method for forming and programming same. The network includes a plurality of independent programmable resistor arrays in a standard DIP semiconductor package. Each resistor array includes a plurality of parallel connected resistor elements capable of being selectively deleted from the array of applying a programming flow of electricity across a first and second DIP pin. The flow of electricity is of a value sufficient to progressively fuse successive array resistors. The total array resistance value progressively increases as array resistors are selectively deleted. Typically an increasing flow of electricity is applied across the array terminals until the desired array resistance value is obtained. The arrays may be manufactured in such a way that the incremental value between successive resistive elements causes the total array resistance value to increase in any desired manner, e.g. geometrically, arithmetically, and logarithmically.Type: GrantFiled: April 13, 1983Date of Patent: August 29, 1989Inventor: John M. Birkner
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Patent number: 4789951Abstract: A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.Type: GrantFiled: May 16, 1986Date of Patent: December 6, 1988Assignee: Advanced Micro Devices, Inc.Inventors: John M. Birkner, Danesh M. Tavana, Andrew K. Chan, Sing Y. Wong
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Patent number: 4554640Abstract: A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates. This allows the product terms to be shared between two outputs.Type: GrantFiled: January 30, 1984Date of Patent: November 19, 1985Assignee: Monolithic Memories, Inc.Inventors: Sing Y. Wong, John M. Birkner
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Patent number: 4476560Abstract: An improved circuit for serial scan diagnosis is provided. A state register in the signal path of the digital system under diagnosis is coupled to a diagnostic shift register. Test data is introduced and removed through the diagnostic shift register through a serial input terminal and serial output terminal. For certain operations the serial input terminal becomes a control terminal whereby a minimum number of control lines is required.Type: GrantFiled: September 21, 1982Date of Patent: October 9, 1984Assignees: Advanced Micro Devices, Inc., Monolithic Memories, Inc.Inventors: Warren K. Miller, Michael J. Miller, John M. Birkner