Abstract: A method and apparatus for increasing the performance of disk drive access by delaying a pending data transfer operation to an individual disk drive until immediately before the start of the target sector so as to allow servicing of an intervening seek operation to another disk drive.

Abstract: A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate.

Abstract: A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.

Abstract: Data processing apparatus wherein circuitry for data transfer between a central processor unit (CPU) and a peripheral storage unit, such as a hard disk storage unit, comprises a data transfer bus by which a block of data words being transferred is supplied to a temporary storage unit capable of storing the entire block. Means are provided to prevent any data transfer between the data bus and the CPU interface unit while the block of data words is transferred between the temporary storage unit and the peripheral storage unit and to permit transfer between the CPU interface unit and the bus when data is not being transferred between the temporary storage unit and the peripheral storage unit.