Patents by Inventor John M. Heumann

John M. Heumann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7424141
    Abstract: A system and method for performing auto-focusing operations for tomosynthetic reconstruction of images are provided. More specifically, embodiments of the present invention provide a system and method for efficiently computing the gradient of one or more depth layers of an object under inspection, wherein such gradients may be used in performing auto-focusing operations to determine a depth layer that includes an in-focus view of a feature that is of interest. In at least one embodiment, a method is provided that comprises capturing detector image data for an object under inspection, and using the detector image data for computing gradient information for at least one depth layer of the object under inspection without first tomosynthetically reconstructing a full image of the at least one depth layer.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 9, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: David Gines, Tracy K. Ragland, John M. Heumann
  • Patent number: 7373332
    Abstract: Techniques for detecting temporal process variation and for managing and predicting performance of automatic classifiers applied to such processes using performance estimates based on temporal ordering of the samples are presented.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: May 13, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: John M. Heumann, Jonathan Q. Li
  • Patent number: 7200534
    Abstract: In one embodiment, a method for designing a radiographic imaging system includes 1) receiving a number of design constraints for the system, and then 2) in response to the constraints, generating a plurality of radiographic imaging system designs, each having a different number of radiographic sources, and each requiring a different number of nominal scan passes to image a specimen region of interest. Designs having a greater number of radiographic sources have sets of translated radiographic detection areas sharing at least some coincident, nominal scan passes as compared to radiographic imaging system designs having fewer radiographic sources. Each set of translated radiographic detection areas is associated with a radiographic source that is replicated and translated with respect to a radiographic source that forms part of a radiographic imaging system design having fewer radiographic sources. Related systems and apparatus are also disclosed.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 3, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: John M. Heumann, Gerald L. Meyer
  • Patent number: 7108424
    Abstract: A calibration technique is presented for calibrating non-reference indirect measurement systems with respect to a reference indirect measurement system. A reference map function filling procedure fits a reference map function based on known values of a parameter of interest associated with reference calibration samples and corresponding reference values associated with the reference calibration samples. A correction function fining procedure fits a correction function based on reference values for calibration samples measured on or simulated for the reference indirect measurement system and corresponding values measured on the non-reference indirect measurement system. During normal use, the non-reference indirect measurement system obtains measurements, corrects the measurements using the correction function, and estimates the parameter of interest of the object of interest using the reference map function based on the corrected measurements.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 19, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: John M. Heumann, Eduardo Acosta
  • Patent number: 7099435
    Abstract: A tomographic reconstruction method and system incorporating Bayesian estimation techniques to inspect and classify regions of imaged objects, especially objects of the type typically found in linear, areal, or 3-dimensional arrays. The method and system requires a highly constrained model M that incorporates prior information about the object or objects to be imaged, a set of prior probabilities P(M) of possible instances of the object; a forward map that calculates the probability density P(D|M), and a set of projections D of the object. Using Bayesian estimation, the posterior probability p(M|D) is calculated and an estimated model MEST of the imaged object is generated. Classification of the imaged object into one of a plurality of classifications may be performed based on the estimated model MEST, the posterior probability p(M|D) or MAP function, or calculated expectation values of features of interest of the object.
    Type: Grant
    Filed: November 15, 2003
    Date of Patent: August 29, 2006
    Assignee: Agilent Technologies, Inc
    Inventors: John M. Heumann, Colin Fox, David Gines, Nicholas Tufillaro
  • Patent number: 6850589
    Abstract: Disclosed are a method and apparatus for tomography of a curved surface in an object. One embodiment is a method that includes determining an expected distortion for each of a plurality of points in a projection of the curved surface, and correcting each of the plurality of points in the projection according to the expected distortion of that point by replacing pixel values in the uncorrected projection with corresponding interpolated pixel values at the expected positions.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: February 1, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: John M. Heumann, David C. Reynolds
  • Patent number: 6765981
    Abstract: A system and method of computed tomography is disclosed. The method includes acquiring at least one projection but less than all projections to be used in reconstruction of an unknown object and processing the at least one projection for reconstruction of the unknown object. After processing each projection is discarded. Projections are acquired until all projections have been processed. An estimate of the unknown object may be generated during the processing of each of the projections.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 20, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: John M Heumann
  • Publication number: 20040022348
    Abstract: A system and method of computed tomography is disclosed. The method includes acquiring at least one projection but less than all projections to be used in reconstruction of an unknown object and processing the at least one projection for reconstruction of the unknown object. After processing each projection is discarded. Projections are acquired until all projections have been processed. An estimate of the unknown object may be generated during the processing of each of the projections.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Inventor: John M. Heumann
  • Publication number: 20030204507
    Abstract: Hierarchical classification of samples. First stage classification identifies most members of the majority class and removes them from further consideration. Second stage classification then focuses on discriminating between the minority class and the greatly reduced number of majority class samples lying near the decision boundary.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 30, 2003
    Inventors: Jonathan Qiang Li, David R. Smith, Lee A. Barford, John M. Heumann
  • Publication number: 20030185339
    Abstract: A device for tomography of curved surfaces is disclosed including a source, an object having a curved surface, and a detector having a curved shape corresponding to the curved surface. Also disclosed are a method and apparatus for tomography of a curved surface in an object, that includes determining an expected distortion for each of a plurality of points in a projection of the curved surface, and correcting each of the plurality of points in the projection according to the expected distortion of that point.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 2, 2003
    Inventors: John M. Heumann, David C. Reynolds
  • Patent number: 6291978
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, the driver of a first test channel applies a test signal to a selected node of the plurality of nodes. A predetermined amount of time after application of the test signal, the receiver of the first test channel reads a node voltage of the selected node. The node voltage is then compared to a predetermined threshold voltage of the receiver of the first test channel, and the result of the comparison is an indication as to whether the selected node is coupled to ground.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6201850
    Abstract: An X-ray inspection system incorporates an improved technique for determining, in an X-ray image of a multilayered assembly, the gray level component of a first material in the presence of a second material. The total gray level of the image is dependent upon the physical characteristics of each material comprising the assembly. The present invention accurately determines the component of the total image gray level due to the first material. In the case of circuit board inspections using X-ray images of solder connections, a calibration procedure facilitates the direct conversion of the gray level component due to the solder connection to the thickness of the solder connection.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: March 13, 2001
    Assignee: Agilent Technologies, Inc.
    Inventor: John M. Heumann
  • Patent number: 6191570
    Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: February 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6051979
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.
    Type: Grant
    Filed: July 25, 1999
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6002739
    Abstract: A cone-beam tomographic system in which computation speed is improved by reducing the reconstructed images to thin planes. Reducing the images to thin planes reduces the number of picture elements to be computed, and reduces basis functions to a simple function of the angle of a ray relative to a plane. In a variation, computation speed is further improved by making pixel size inversely proportional to the distance of a plane from an emissions source. As a result of the variable pixel size, for each projection, a ray intersecting the center of a sensor element intersects the center of exactly one pixel in each object plane.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: December 14, 1999
    Assignee: Hewlett Packard Company
    Inventor: John M. Heumann
  • Patent number: 5977775
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node, at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: November 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5922079
    Abstract: An automated analysis system that identifies detectability problems, diagnosability problems, and possible ways to change rank order of diagnoses in a diagnostic system and makes the problems and possible improvements visible to test programmers to aid in test improvement. Components that have no coverage and components that have inadequate coverage (according to a heuristic criteria) are identified as potential detectability problems. Components that are exercised by identical operations in all tests are identified as diagnosability problems. If an incorrect diagnosis is made, the automated analysis system identifies failing tests that have no coverage of any component in the true failure cause. In addition, if an incorrect diagnosis is made, the automated analysis system identifies ways of changing the rank order of diagnoses, including coverages that can be reduced and identification of operation violations that can be eliminated or deliberately added.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: July 13, 1999
    Assignee: Hewlett-Packard Company
    Inventors: George L. Booth, John M. Heumann, Douglas R. Manley
  • Patent number: 5504432
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 2, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5489851
    Abstract: A method and apparatus for determining whether semiconductor components are electrically connected to a printed circuit board. A voltage (or current) is connected to two traces leading to connections to a semiconductor component to be tested. The initial current (or voltage) is measured at an initial temperature. Then, the temperature of the semiconductor is changed. Current (or voltage) is measured again after the temperature change. A change in current (or voltage) indicates that the semiconductor component is electrically connected to the trace.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: February 6, 1996
    Assignee: Hewlett-Packard Company
    Inventors: John M. Heumann, Ronald J. Peiffer
  • Patent number: 5469064
    Abstract: The present invention is an improved printed circuit board test system in which test probes are positioned to electronically engage a selected device or printed circuit board section on a printed circuit board for testing the printed circuit board for manufacturing defects. The printed circuit board test system uses a bed-of-nails test fixture to ground and excite predetermined sites on a first side of the printed circuit board and a robot to mechanically position test probe(s) at selected test sites on a second side of the printed circuit board. A controller is used to control the movement of the robotic tester and the selection of spring probes in the bed-of-nails fixture to be exited, grounded or measured.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: November 21, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Ronald K. Kerschner, John M. Heumann, John E. McDermid, Ed. O. Schlotzhauer, David T. Crook