Patents by Inventor John M. Morgan
John M. Morgan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11998258Abstract: An energy module for driving electrosurgical and/or ultrasonic surgical instruments is disclosed. The energy module can include an amplifier assembly that is configured to drive a variety of different energy modalities for one or more surgical instruments connected thereto. The energy module can further include a relay assembly for selectively coupling one or more of the amplifiers to different ports to which the surgical instruments are connectable. The amplifier assembly can include amplifiers for driving ultrasonic, bipolar, and/or monopolar energy.Type: GrantFiled: September 5, 2019Date of Patent: June 4, 2024Assignee: Cilag GmbH InternationalInventors: Joshua Henderson, Joshua P. Morgan, Eitan T. Wiener, Ryan M. Asher, Brendan J. Oberkircher, John B. Schulte, John E. Hein, James R. Hoch
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Patent number: 11911039Abstract: A surgical stapler instrument includes a stapling head assembly that receives a plurality of staples. The staples are configured with features that allow the staples to expand after deployment so that an anastomosis created by the instrument can increase in size after forming. In some versions the staples expand automatically after deployment, and in other versions the staples expand in response to tissue forces imparted upon the staples after deployment. In some versions the staples are configured to be deployed in various patterns that promote expandability of the circular staple line.Type: GrantFiled: August 13, 2021Date of Patent: February 27, 2024Assignee: Cilag GmbH InternationalInventors: Chad P. Boudreaux, Jeffrey L. Aldridge, Nicholas M. Morgan, Michael J. Stokes, Marissa T. Kamenir, John K. Bruce, John S. Kimsey, Yvan D. Nguetio Tchoumkeu
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Patent number: 10133697Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U) implementation, a four rack unit (4U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.Type: GrantFiled: August 16, 2017Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Dirk F. Blevins, John M. Morgan, Marc A. Goldschmidt, Edward J. Pullin
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Publication number: 20180024955Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U) implementation, a four rack unit (4U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.Type: ApplicationFiled: August 16, 2017Publication date: January 25, 2018Inventors: Dirk F. Blevins, John M. Morgan, Marc A. Goldschmidt, Edward J. Pullin
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Patent number: 9792243Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.Type: GrantFiled: December 26, 2013Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Dirk F. Blevins, John M. Morgan, Marc A. Goldschmidt, Edward J. Pullin
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Publication number: 20170082687Abstract: A method performed on a user interface device is described. The method includes connecting to a smart card where the smart card is connected to an electronic system to be de-bugged. The method also includes causing a cloud service to download customized test vectors for the electronic system to the smart card. The method also includes causing the smart card to begin execution of test software and/or operation of programmable hardware logic circuitry that uses the customized test vectors to test the electronic system.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: ROLAND W. KLINGER, DIRK F. BLEVINS, JOHN M. MORGAN, ERIC D. HEATON, AI BEE LIM, LIANG-MIN WANG
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Patent number: 9361233Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.Type: GrantFiled: December 20, 2013Date of Patent: June 7, 2016Assignee: INTEL CORPORATIONInventors: Liang-Min Wang, John M. Morgan, Namakkal N. Venkatesan
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Publication number: 20150186319Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Dirk F. Blevins, John M. Morgan, Marc A. Goldschmidt, Edward J. Pullin
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Publication number: 20150178199Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Liang-Min Wang, John M. Morgan, Namakkal N. Venkatesan
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Patent number: 4881574Abstract: An enclosed rotary disc air pulser for use with a solvent extraction pulse olumn includes a housing having inlet, exhaust and pulse leg ports, a shaft mounted in the housing and adapted for axial rotation therein, first and second disc members secured to the shaft within the housing in spaced relation to each other to define a chamber therebetween, the chamber being in communication with the pulse leg port, the first disc member located adjacent the inlet port, the second disc member being located adjacent the exhaust port, each disc member having a milled out portion, the disc members positioned on the shaft so that as the shaft rotates, the milled out portions permit alternative cyclical communication between the inlet port and the chamber and the exhaust port and the chamber.Type: GrantFiled: August 12, 1988Date of Patent: November 21, 1989Assignee: The United States of America as represented by the Department of EnergyInventors: A. L. Olson, Tom A. Batcheller, J. A. Rindfleisch, John M. Morgan
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Patent number: 4514004Abstract: A device for snagging a length of free-hanging flexible wire at an end and retaining the wire therein as the wire is routed across an inaccessible area. The device comprises an angulated hook having a pair of opposed edges meeting in an acute angle. The edges are provided with friction means positioned to face the interior region of the angulated hook for holding a wire or the like in the apical region of the hook. In the preferred embodiment the edges are provided by the opposing sides of a pair of elongate arms, and the friction means is provided by a pair of longitudinally extending planar surfaces meeting at an apex to define a knife-edge on the inner side of each arm, the knife-edges being positioned to oppose one another so that a length of wire snagged between the arms will be retained there by friction with the knife-edges.Type: GrantFiled: July 14, 1983Date of Patent: April 30, 1985Inventor: John M. Morgan
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Patent number: 3995246Abstract: A device for controlling the temperature and protecting against excessive flow of current of electric installations, said device being provided with a mechanical switch which opens itself at a definite previously selected temperature, said mechanical switch comprising cylindrical housing wherein two elastic contact means are provided, one of the contact means comprising an open spring spiral torsion with bent ends which is provided around a melting body of thermally softenable material and is pressed with a tension directly against the spring action of the other contact means.Type: GrantFiled: February 4, 1975Date of Patent: November 30, 1976Inventor: John M. Morgan