Abstract: A data corruption indicator circuit for providing error free data transfer between a first device and a second device, clocked by different clock signals, is implemented. The data corruption indicator circuit can allow for faster throughput than the described prior art and provides a circuitry for detecting corrupt data. The data corruption indicator circuit provides a clocked data ready signal that updates a status lip-flop and a delayed data ready signal that updates a plurality of data flip-flops and a potential corruption flip-flop. Additionally, the delayed data ready signal may be used as an interrupt signal to notify the second device that data is available for transfer. The delay between the clocked data ready signal and the delayed data ready signal is such that a hazard cannot exist for the data signal and the status signal simultaneously.

Abstract: A computer system having dual paths for controlling a peripheral device electrically associated with a host computer. The peripheral device is electrically connected to the host computer and to an independent control circuit. Control inputs for the peripheral device and data and/or control inputs for the host computer are generated by a keyboard or other input device and transmitted to an input controller which directs certain data and/or control inputs to the host computer for processing and directs certain peripheral device control inputs to a state machine for the generation of peripheral device control signals. In such a manner, the independent control circuit provides for the control of the peripheral device while the host computer may process data unrelated to the control of the peripheral device. In one aspect, control of the peripheral device may be effected by both the host computer and the independent control circuit.

Abstract: An information processing system such as a microprocessor includes a processor core, a debug register circuit and a trace unit. The processor core is for processing information according to a program. The program includes a plurality of instructions for execution by the processor core. Each of the plurality of instructions has a corresponding address. The debug register circuit is coupled to the processor core. The debug register circuit includes a dedicated initiate trace breakpoint register coupled to receive and store an initiate trace address and a dedicated terminate trace breakpoint register coupled to receive and store a terminate trace address. The trace unit is coupled to the debug register circuit and the processor core. The trace unit initiates a program trace responsive to the program accessing the initiate trace address. The trace unit terminates the program trace responsive to the program accessing the terminate trace address.

Abstract: A computer system having dual paths for controlling a peripheral device electrically associated with a host computer. The peripheral device is electrically connected to the host computer and to an independent control circuit. Control inputs for the peripheral device and data and/or control inputs for the host computer are generated by a keyboard or other input device and transmitted to an input controller which directs certain data and/or control inputs to the host computer for processing and directs certain peripheral device control inputs to a state machine for the generation of peripheral device control signals. In such a manner, the independent control circuit provides for the control of the peripheral device while the host computer may process data unrelated to the control of the peripheral device. In one aspect, control of the peripheral device may be effected by both the host computer and the independent control circuit.