Abstract: A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.

Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.

Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.