Abstract: A functional testing system for programmable logic devices. Test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs. The logic level on pins that are outputs are controlled by the logic device, while logic levels on pins that are inputs are controlled by the shift register. The response of the logic device to the test vector is recorded in an output shift register and the response is then shifted out of the shift register to one input of an exclusive OR gate that also receives outputs from predetermined stages of the test vector shift register to create a pseudo-random function. The output of the exclusive OR gate is shifted into the test vector shift register as each bit of the logic device's response is applied to the exclusive OR gate thereby creating a new test vector.

Abstract: A signature analyzer for testing digital circuits. The analyzer includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node.