Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

Abstract: Embodiments disclosed herein include reticles for extreme ultraviolet (EUV) lithography and methods of forming such reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer includes alternating layers of a first mirror layer and a second mirror layer. In an embodiment, a fiducial may be formed into the mirror layer. In an embodiment, the fiducial comprises constituents of the first mirror layer and the second mirror layer. In an embodiment, an absorber layer may be formed over the mirror layer.

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

Abstract: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.

Abstract: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.

Abstract: In one embodiment, a metallic micro-cantilever, comprises a silicon substrate, at least one via plug extending from a surface of the silicon substrate, a metallic layer cantilevered from the at least one via plug, and a metallic probe tip extending from a surface of the metallic layer.

Abstract: A liquid crystal over silicon light modulator may include a trenched cover glass. The trenched cover glass enables the provision of regions between adjacent dice on the wafer level. These regions facilitate sealing of the individual modulators and dicing of the individual modulators from the overall wafer. In some embodiments this may reduce contamination of the liquid crystal with the sealing material and losses at the dicing stage.