Abstract: The present invention relates to a multilayer wiring structure for a semiconductor device which can be designed without sacrificing either a micronization or electric properties, and a manufacturing method of the same. A first wiring layer and a third wiring layer are connected by a lower layer contact plug which fills a lower layer contact hole interposing a silicon nitride film spacer, and an upper layer contact plug which fills an upper layer contact hole interposing a silicon oxide film spacer. A second wiring layer divided into more than two portions by the upper layer contact hole near an upper end of the lower layer contact hole is connected by a ring-shaped conductive film spacer.

Abstract: A fabrication method of a semiconductor device is provided, which eliminates the effects of polishing residue generated by a CMP process. A first layer having a hole is prepared, where the first layer may be formed directly on a surface of a semiconductor substrate or formed over a surface of a semiconductor substrate through at least one layer. A second layer is then formed to cover the hole. The hole is not filled with the second layer to thereby form a gap on the second layer. A protection layer is formed on the second layer so that the gap is filled with the protection layer. The protection layer and the second layer are removed by a CMP process until the first layer is exposed, thereby selectively leaving the protection layer and the second layer in the hole. The second layer left in the hole serves as a plug. A third layer is formed on the second layer to cover the plug. Preferably, a step of selectively removing the protection layer left in the gap is additionally provided prior to the CMP process.

Abstract: An interconnection system in a semiconductor device comprises a Ti.sub.2 N film having a lower resistivity and a higher thermal stability at a higher temperature compared to a TiN film. The Ti.sub.2 N film is formed by rapid thermal annealing of a TiN film and a Ti film consecutively formed on an insulator film. The rapid thermal treating is effected in a nitrogen ambient at a substrate temperature of 700 to 900.degree. C. for 30 to 120 seconds.

Abstract: A semiconductor device has a contact plug made of a material other than tungsten, i.e., Ti and TiN films, and an interconnection pattern made of sputtered tungsten and connected to a silicon substrate through the contact plug. The tungsten film has mainly (200) and (211) orientations on the top of the insulator film to reduce the resistivity of the tungsten and has mainly (110) orientation on the exposed regions of the Ti and TiN films at the top of the contact plug.

Abstract: A formation method of a contact/through hole is provided, which is able to form a contact or through hole without raising such problems related to a resist mask. After forming a dielectric layer on a semiconductor substructure having a lower electrical conductor, a metal layer is formed on the dielectric layer. A patterned resist film is formed on the metal layer. Then, the metal layer is selectively etched using a patterned resist film as a mask to transfer the pattern of the resist film to the metal layer, forming a hole pattern to penetrate the metal layer. The patterned resist film is removed from the etched metal layer. The dielectric layer is selectively etched using the etched metal layer as a mask to thereby transfer the hole pattern of the metal layer to the dielectric layer. Thus, a contact/through hole is formed to penetrate the dielectric layer and to extend to the lower electrical conductor.

Abstract: A storage node electrode is connected to a contact plug via an upper node contact hole. A lower cell plate electrode composed of an N type silicon film and an N type silicon film spacer is covered by the storage node electrode via a titanium oxide film as a lower capacitive insulating film and an upper cell plate electrode composed of an N type silicon film connected to the lower cell plate electrode covers the storage node electrode via a titanium oxide film as an upper capacitive insulating film. Thus, in a DRAM having a stacked and COB type memory, a surface ratio of the storage node electrode, contributing to a capacitor, is increased.

Abstract: A storage node electrode is connected to a contact plug via an upper node contact hole. A lower cell plate electrode composed of an N type silicon film and an N type silicon film spacer is covered by the storage node electrode via a titanium oxide film as a lower capacitive insulating film and an upper cell plate electrode composed of an N type silicon film connected to the lower cell plate electrode covers the storage node electrode via a titanium oxide film as an upper capacitive insulating film. Thus, in a DRAM having a stacked and COB type memory, a surface ratio of the storage node electrode, contributing to a capacitor, is increased.

Abstract: The present invention relates to a multilayer wiring structure for a semiconductor device which can be designed without sacrificing either a micronization or electric properties, and a manufacturing method of the same.A first wiring layer and a third wiring layer are connected by a lower layer contact plug which fills a lower layer contact hole interposing a silicon nitride film spacer, and an upper layer contact plug which fills an upper layer contact hole interposing a silicon oxide film spacer. A second wiring layer divided into more than two portions by the upper layer contact hole near an upper end of the lower layer contact hole is connected by a ring-shaped conductive film spacer.