Patents by Inventor John McCollum

John McCollum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile programmable memory cell for programmable logic array
    Patent number: 7590000
    Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: September 15, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Hung-Sheng Chen, Frank Hawley
  • NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
    Publication number: 20090212343
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Application
    Filed: April 2, 2009
    Publication date: August 27, 2009
    Applicant: ACTEL CORPORATION
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7573093
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 11, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
    Publication number: 20090189634
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 30, 2009
    Inventors: Sana Rezgui, John McCollum, Jih-Jong Wang
  • NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
    Publication number: 20090159954
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Application
    Filed: January 26, 2009
    Publication date: June 25, 2009
    Applicant: ACTEL CORPORATION
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • RADIATION TOLERANT SRAM BIT
    Publication number: 20090141539
    Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
    Type: Application
    Filed: December 29, 2008
    Publication date: June 4, 2009
    Applicant: Actel Corporation
    Inventor: John McCollum
  • Non-volatile look-up table for an FPGA
    Patent number: 7538576
    Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: May 26, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Gregory Bakker, Jonathan Greene
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7538379
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: May 26, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors
    Patent number: 7538598
    Abstract: A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: May 26, 2009
    Assignee: Actel Corporation
    Inventor: John McCollum
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7538382
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: May 26, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7501681
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 10, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
    Publication number: 20090057821
    Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
    Type: Application
    Filed: October 27, 2008
    Publication date: March 5, 2009
    Applicant: ACTEL CORPORATION
    Inventors: A. Farid Issaq, Frank Hawley, John McCollum
  • Flash/dynamic random access memory field programmable gate array
    Patent number: 7499360
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: March 3, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker
  • Non-volatile look-up table for an FPGA
    Patent number: 7495473
    Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 24, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Gregory Bakker, Jonathan Greene
  • Non-volatile look-up table for an FPGA
    Patent number: 7492182
    Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 17, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Gregory Bakker, Jonathan Greene
  • Programmable system on a chip
    Patent number: 7487376
    Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 3, 2009
    Assignee: Actel Corporation
    Inventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
  • Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge
    Patent number: 7482218
    Abstract: A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to said first conductivity type is disposed in the well. A pair of opposed source regions doped to the second conductivity type are disposed in the well and are electrically coupled together. They are separated from opposing outer edges of the drain region by channels. A pair of gates are electrically coupled together and disposed above and insulated from the channels. A region of the well disposed below the drain is doped so as to reduce capacitive coupling between the drain and the well.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: January 27, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Fethi Dhaoui
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7473960
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 6, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material
    Patent number: 7459763
    Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: December 2, 2008
    Assignee: Actel Corporation
    Inventors: A. Farid Issaq, Frank Hawley, John McCollum
  • FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY
    Publication number: 20080279028
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Application
    Filed: July 29, 2008
    Publication date: November 13, 2008
    Applicant: ACTEL CORPORATION
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker