Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: Techniques relating to aligning data bits in frequency synchronous data channels are disclosed. The techniques include determining a phase relationship between clock signals in a pair of data channels. If the clock signals are determined to be out-of-phase, the data bits in a particular one of the data channels may be reordered.

Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.

Abstract: In accordance with the present invention, circuits are disclosed for use in implementing higher order sigma delta analog to digital conversion of narrowband signals with cascaded lower order circuit networks. The lower order circuit networks employ resonator circuits utilizing unit delay functional blocks to implement a specific transfer function. The unit delays are implemented utilizing sample and hold circuits operated by controlled switching of the circuit elements. In one embodiment, the resonator circuit includes a first sample and hold circuit for implementing a unit delay of corresponding input signals where the output of the first sample and hold circuit is coupled into a feedback loop with one or more additional sample and hold circuits for implementing a dual cascaded unit delay. The delayed signals from the feedback loop are then summed with the input signals at the input of the first sample and hold circuit.

Abstract: A circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed. The stabilization circuit is formed to generate a reference current that is proportional to a reference capacitance C.sub.S and the thermal voltage V.sub.T. The reference current is ultimately mirrored (as the bias current) into the bipolar devices which determine the gm within the analog circuit. Since the transconductance gm of a bipolar device can be expressed as collector current, I.sub.C, divided by V.sub.T, the thermal voltage factor of the bias current itself will "cancel" the thermal voltage factor present in the transconductance. The effects related to the remaining variable, the capacitance, will be eliminated as long as the reference capacitance is formed to "track" the analog circuit capacitance by using similar types of capacitance to implement both capacitors and forming both the stabilization circuit and the analog circuit on the same silicon chip.