Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

Abstract: Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.

Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

Abstract: This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest neighbors,” with values calibrated and used for each particular transmitter-receiver pair. Embodiments are also presented which address crosstalk induced between lines that are not nearest neighbors, such as, for example, for use in a differential signaling system.

Abstract: This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest neighbors,” with values calibrated and used for each particular transmitter-receiver pair. Embodiments are also presented which address crosstalk induced between lines that are not nearest neighbors, such as, for example, for use in a differential signaling system.

Abstract: A vehicle is adapted to operate on land and in water having a depth of over four feet. The vehicle includes a chassis, one or more pontoons supported by the chassis, and a track system disposed on each of the one or more pontoons and adapted to provide propulsion to the vehicle. Each pontoon has a height of at least four feet, a width and a length adjacent to the land, wherein a ratio of the height to the width exceeds 1.4, and a volume configured to provide buoyancy and support the chassis weight.

Abstract: Methods and devices for providing flexible electronics are described. In an exemplary embodiment of the present invention, a conductive ink is applied to a nonwoven substrate. More particularly, the exemplary embodiment provides a nonwoven substrate with a general depth in the z-direction and a conductive ink carried by the nonwoven substrate on the surface of the substrate and at least partially but no more than 50% within the nonwoven substrate in the z-direction.

Abstract: A vehicle is adapted to operate on land and in water having a depth of over four feet. The vehicle includes a chassis, one or more pontoons supported by the chassis, and a track system disposed on each of the one or more pontoons and adapted to provide propulsion to the vehicle. Each pontoon has a height of at least four feet, a width and a length adjacent to the land, wherein a ratio of the height to the width exceeds 1.4, and a volume configured to provide buoyancy and support the chassis weight.

Abstract: In order to synchronise video and audio signals, a video test signal and an audio test signal are generated at the transmitting end of a transmission link, and transmitted over the link. The video test signal has first and second active picture periods of contrasting states. The audio test signal has first and second periods of contrasting states. As generated, the video and audio test signals have a predetermined timing relationship—for example, their changes of respective states may be coincident in time. At the receiving end of the link, the video and audio test signals as received are detected, and any difference of timing between the video and audio test signals is derived from their changes of respective states, measured and displayed, including an indication of whether the video signal arrived before the audio signal or vice-versa.

Abstract: The present invention provides cement compositions comprising an improved fluid loss control additive, and methods for cementing in a subterranean formation using such cement compositions. The cement compositions comprise a hydraulic cement, water, and a fluid loss control additive comprising at least two polymers connected by a pH-sensitive crosslink. Optionally, other ingredients may be included in the compositions.

Abstract: The chassis connects adjacent flotation members each having supports projecting therefrom for attaching to the chassis. The chassis includes a pair of beams having opposite ends and sides with an end flange affixed to the ends of the beams. A plate is affixed to one of the opposite sides of the beams and has a length greater than the beams to form extension surfaces at each end. The extension surfaces are connected to the supports on a first plane and the end flanges are connected to the supports on another plane, preferably perpendicular to the first plane and vertical to the ground. The beams are preferably I-beams having a web and opposing extending sides perpendicular to the web. The top side is longer than the web and other side so as to form a tine which is received in a recess in the end flanges.