Abstract: A variable bandwidth filter is described herein, wherein a bandwidth of a passband of the variable bandwidth filter is dynamically tunable. The variable bandwidth tuner is implemented on a CMOS chip, and acts to filter analog signals. The variable bandwidth filter comprises a plurality of finite impulse response (FIR) filters, wherein each FIR filter comprises a plurality of tunable transconductors. The tunable transconductors are tunable in their gain.

Abstract: Described herein is a power-efficient Gm-C filter, wherein the Gm-C filter includes several operational transconductance amplifiers (OTAs). In an example, at least two of the OTAs share a common bias current. Further, output of one of the OTAs is used to bias another one of the OTAs. Also described herein is a power-efficient clock generator circuit that is configured to output non-overlapping clock signals. The clock generator circuit includes a ring oscillator circuit, which includes several inverter stages. The clock generator circuit is well-suited for controlling operation of switches.

Abstract: Described herein are various technologies relating to processing a coherent signal. A receiver is configured to receive an analog signal, and process the analog signal to generate an input analog signal. The input analog signal has been modulated according to a suitable modulation sequence. A coherent signal sampler coherently samples the modulation sequence, and the result of such sampling is in turn used to demodulate the input analog signal. The resultant signal is then passed to a sigma delta modulator, where it is converted to digital form.