Abstract: A surgical port for protecting nearby tissue is described. In one example, the port includes a base portion connected to a hollow tubular portion having a beveled end. The base portion is sized and shaped to protect the surrounding tissue from heat and friction. The base portion may include one or more holes for receiving sutures to releasably secure the surgical port to the body during use. The beveled end of the tubular portion facilitates lateral movement of surgical instruments toward the short side of the bevel. The base portion may include an indicator such as a notch that provides a visual and tactile cue to the surgeon about the orientation of the beveled end. Using the indicator as a guide, the surgeon can release and rotate the surgical port to another orientation without removing it from the body and re-inserting it.

Abstract: Built-in self-testing of embedded logic circuitry at the output of an on-chip memory array is presented. Testing is accomplished by generating on chip a test pattern which is provided to the logic circuitry by writing at least a portion thereof into the memory array and then reading that portion out of the memory array, to the embedded logic circuitry. Three specific embodiments are presented, each of which employs a deterministic looping test pattern that comprises a portion of the generated test pattern. The looping test pattern may be either written through the memory array to the embedded logic circuitry or written around the memory array directly to the logic circuitry.

Abstract: A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.

Abstract: A space dividing panel system having a plurality of panels. Slotted standards are disposed between adjacent panels, with each slotted standard having first and second vertical rows of slots respectively accessible from opposite sides of the panels. A counter cap is disposed in spaced relation above an upper edge of a panel, supported by at least one support assembly. The upper edge of the panel includes an upwardly open wire trough. The support assembly includes first and second bracket members respectively supported by the first and second vertical rows of slots. A third bracket member is fixed to the first and second bracket members, and the counter cap is fixed to the third bracket member. The spaced relation between the counter cap and the upper edge of the wire trough provides access to the wire trough without disturbing the support assembly or counter cap.

Abstract: An electrical or communications monument for selective mounting along an edge of a work surface which may have a predetermined minimum spacing between the edge and an adjacent obstruction. The monument includes a one-piece bracket having a back portion from which a base and first and second spaced support arms extend. The base joins the back portion with a curved section which has a predetermined relative large radius. The back portion extends above the support arms to provide a flange upon which a receptacle is mounted. The curved section enables the bracket to be mounted along an edge of a work surface, notwithstanding a closely spaced wall, with the support arms resting upon the work surface. A screw is threadedly engaged with the base. Engagement of the screw with the lower side of the work surface provides a firm three-point support for the monument.

Abstract: Interface circuitry for obtaining simultaneous, multi-channel analog outputs from a microprocessor, avoiding sequential addressing delays. The technique involves inserting, for each analog output channel, a buffer latch between the data bus lines from the microprocessor and the D/A latch associated with the D/A converter. The buffer latches are sequentially addressed by control logic circuitry and loaded from the computer memory in accordance with software instructions in the microprocessor. While data is being loaded in the buffer latches, the D/A latches are disabled, preventing the data from being presented to the D/A converters. When all channels are loaded, the D/A latches are strobed simultaneously, enabling them and transferring the data stored in the buffer latches to the D/A converters for conversion to analog outputs.

Abstract: A solid state data recording system for storing multichannel analog data. is low power system has characteristics similar to a high performance analog tape recorder but has no moving parts and can be easily ruggedized for severe environmental conditions. In the "write" mode analog data are sampled and converted to digital bits of information. These individual bits are stored in a solid state storage medium by coded enabling and address information provided by a controller. The information is played back by reading out these digital bits, converting them to analog form, and then demultiplexing them to their original channels.