Abstract: A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

Abstract: A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

Abstract: A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input data signal and compares the input data signal to the digital value stored in the comparator. A comparison signal is generated in response to the comparison. The comparison signal from each comparator is received by an end cell which also receives the comparison signal from the immediately adjacent comparator. The end cell generates an output signal. An end cell is associated with each comparator. The plurality of output signals from the end cells represent the location of the comparator which borders the value of the input data signal.

Abstract: According to the invention, the electrical charge which is transferred to a circuit node by the switching ON or OFF of a field effect transistor whose source or drain is connected to that node is cancelled by connecting the source and drain of another field effect transistor to that circuit node and applying to its gate terminal a complement of the switching signal applied to the gate electrode of the first field effect transistor.

Abstract: A balanced differential capacitively decoupled charge sensor for detecting small amounts of charge comprises balanced differential sensing means adapted to receive charge representing data and charge representing a reference value, a pair of capacitance decoupling transistors, the respective drains of each of said pair of capacitance decoupling transistors being electrically coupled to the respective inputs of said differential sensing means, a matched pair of charge output nodes electrically coupled to the respective sources of said capacitance decoupling transistors and adapted to receive, respectively, data charge and reference charge, and means for biasing and resetting both of said charge output nodes so that said capacitance decoupling transistors are functioning in a high transconductance mode when data charge and reference charge are received.