Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: Reduced instruction set computer (RISC) processor based disk manager architecture for HDD (Hard Disk Drive) controllers. Disk manager operations of a HDD are off-loaded from a main processor to a dedicated RISC processor. The main processor is operable to provide higher level instructions to the RISC processor, and the RISC processor is operable to translate those higher level instructions into bit level instructions that are subsequently provided to one or more control engines that is then operable to execute those bit level instructions to perform one or more channel interfacing protocol control functions that can include any one or more of low level timing for servo demodulation, timing for data formatting operations, media control operations, transfer control operations, and/or other disk manager related functions.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Multiple cyclic redundancy check (CRC) engines for checking/appending CRCs during data transfers. Two distinctly implemented CRC engines are employed to enable the processing of different sized byte formats at two ends of a communication channel. These two distinctly implemented CRC engines can be employed to enable the processing of different sized byte formats in a host device at one end and an hard disk drive (HDD) at another end. For example, sometimes the size of blocks, frames, and/or sector sizes that are processed and employed within a first communication device at one end of a communication channel can differ from the size of blocks, frames, and/or sector sizes that are processed and employed within a second communication device at another end of the communication channel. Two distinctly implemented CRC engines allow the appropriate processing and translation of any desired different sized blocks, frames, and/or sector sizes of a communication channel.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Error correction code (ECC) decoding architecture design using synthesis-time design parameters. An approach is presented herein by which an ECC decoding architecture can be designed using synthesis-time design parameters. The manner presented herein allows for a designer to arrive at an ECC decoding architecture in a more direct, straightforward manner that using prior art means. A number of considerations (e.g., architecture parameters, semi-soft design constraints, parallel implementation, etc.) are initially provided; certain or all of these considerations can be predetermined, determined adaptively, and/or modified during the design process. A designer is provided a means by which a most desirable ECC decoding architecture can be arrived at relatively quickly.

Abstract: A system and method identifies and masks physical sectors where the errors encountered during the defect scan exceed a predetermined level. This avoids the need to read and process all the data written to an individual sector during the initial defect scan. This method first writes a predetermined pattern such as a 2-T pattern to the magnetic media available for user data. This written pattern is then read. As the pattern is read, an error result increments or decrements a counter based on the error. The counter reaching a predetermined level signifies that there are too many errors in this physical sector. This sector may then be added to the primary defect list and masked out without reading the remaining written pattern within the sector. This will result significant time savings as physical sectors containing multiple errors are identified without process all the information written to the physical sector.

Abstract: Formatting disk drive data using format field elements (FFEs). A processing module (which can be a general purpose processor or a RISC (Reduced Instruction Set Computer) processor) is employed to generate FFEs that are employed to govern operation of the various data formatting modules within a formatting system within a HDD. The determination of when a data formatting module stops operating in accordance with a first FFE and begins operating in accordance with a second FFE can be a predetermined period of time, a number of operations being performed, the meeting of some condition, or some other means. Each FFE can be viewed as being a multi-dimensional instruction that not only includes a configuration for a data formatting module, but also includes the conditions by which the configuration is to be governed by a subsequent FFE, among other things.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures segregation of scrambled user information, modulation redundancy bits, and RS redundancy bits in such a way that each of the components thereof are segregated and stored within any desirable digital information memory storage device. By providing this segregated capability, when accessing a portion of a RS codeword from the memory, an entire RS codeword need not be read from the memory. In fact, only the particular field (or bits) needs to be accessed to perform correction thereon. This segregation provides for a reduction in the hardware complexity of translation between user information and a modulation codeword. Also, this segregation provides for the ability to perform correction of only one of the scrambled user information, the modulation redundancy bits, or the RS redundancy bits.

Abstract: A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.

Abstract: Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: Formatting disk drive data using format field elements (FFEs). A processing module (which can be a general purpose processor or a RISC (Reduced Instruction Set Computer) processor) is employed to generate FFEs that are employed to govern operation of the various data formatting modules within a formatting system within a HDD. The determination of when a data formatting module stops operating in accordance with a first FFE and begins operating in accordance with a second FFE can be a predetermined period of time, a number of operations being performed, the meeting of some condition, or some other means. Each FFE can be viewed as being a multi-dimensional instruction that not only includes a configuration for a data formatting module, but also includes the conditions by which the configuration is to be governed by a subsequent FFE, among other things.

Abstract: Multiple cyclic redundancy check (CRC) engines for checking/appending CRCs during data transfers. Two distinctly implemented CRC engines are employed to enable the processing of different sized byte formats at two ends of a communication channel. These two distinctly implemented CRC engines can be employed to enable the processing of different sized byte formats in a host device at one end and an hard disk drive (HDD) at another end. For example, sometimes the size of blocks, frames, and/or sector sizes that are processed and employed within a first communication device at one end of a communication channel can differ from the size of blocks, frames, and/or sector sizes that are processed and employed within a second communication device at another end of the communication channel. Two distinctly implemented CRC engines allow the appropriate processing and translation of any desired different sized blocks, frames, and/or sector sizes of a communication channel.

Abstract: A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.