Abstract: A multiple information decoding system and method are provided in which multiple information content is decoded sequentially and provided to a viewer such that the viewer perceives the information content as being simultaneously decoded. One embodiment of the system and method is in a video display system where RF channels are decoded by a single tuner for concurrent presentation to a display.

Abstract: A multiple information decoding system and method are provided in which multiple information content is decoded sequentially and provided to a viewer such that the viewer perceives the information content as being simultaneously decoded. One embodiment of the system and method is in a video display system where RF channels are decoded by a single tuner for concurrent presentation to a display.

Abstract: The invention is a multiple mode transmission system that interconnects the computer of a user with the Internet. The system has a first link that is a relatively low bandwidth telephone system. The system also has a second link that is a relatively high bandwidth television system. The television link can be either terrestrial or cable. The user would send an information request to the Internet across the telephone system. The actual information would be sent to the user via the television system. Scheduling data that informs the user of the time, channel, and exact location of the information in the television signal is sent to the user across the telephone system. The scheduling data is used by the inventive system to program the TV tuner that is used by the computer to receive the TV signal. The information can be encrypted, and the key would be included with the scheduling data. The channels can be dedicated data channels.

Abstract: Disclosed is a system and method for providing full monotonicity among desired sequential output values by converting a stream of sequential input signals each of which are representative of their corresponding desired output values. The disclosed invention comprises a system and method for individually translating each received signal to a unary value, the unary value being representative of a desired output value, and a system and method for selectively enabling a plurality of energy sources as a function of this unary value such that the total of any enabled energy source at any one time is proportional to this unary value. The conversion circuit uses a shifting array for controlling the energy sources.

Abstract: There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The individual bits of each word serve to control the individual system elements. The memory is programmed to allow each group of words to control the system timing in a different manner. Provision is made for the memory to skip certain words in a particular group under control of externally provided signals.

Abstract: There is disclosed a memory controller for controlling addresses to a plurality of different memory types while treating the memory system as a whole so as to create a unified addressing arrangement. The controller is structured to allow for a reprogramming of the split address between the memories and for maintaining contiguously addressed locations. A register is used to hold the split address and the register can be updated at initialization to vary the split depending upon physical memory changes. The controller also maintains a common bit length addressing word regardless of the memory size being addressed by the system processor.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: The invention pertains to semiconductor circuitry, and more particularly to a class of circuitry known as current controlled gate circuits for driving very large scale integrated circuit gate arrays; the novel circuit can achieve much lower speed-power products than other circuitry, such as the well known T.sup.2 L circuitry; the circuit includes push-pull drive and it provides negligible DC current in both DC states, that is, On and Off.

Abstract: Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

Abstract: Logic circuit means for providing a binary output which is a predetermined logical function of a plurality of binary inputs, said logic circuit means including: at least first, second and third push-pull Darlington current sink (PPDCS) logic circuits, each said PPDCS logic circuit comprising: first, second and third transistors, each of said first, second and third transistors having an emitter, base and collector, said collector of said third transistor connected to a first source of potential and said emitter of said second transistor connected to a third source of potential; input circuit means, said input circuit means being adapted to receive n binary inputs, where n is a positive integer having a magnitude of two or greater, said input circuit means being connected to said collector of said first transistor and said base of said third transistor; a first resistor connected between said emitter of said first transistor and a second source of potential; a second resistor connected between said first sourc