Abstract: A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.

Abstract: Systems and methods for controlling a process applied to a substrate within a plasma chamber are described. The systems and methods include generating and supplying odd harmonic signals and summing the odd harmonic signals to generate an added signal. The added signal is supplied to an electrode within the plasma chamber for processing the substrate. The use of odd harmonic signals facilitates high aspect ratio etching of the substrate.

Abstract: An impedance matching circuit (IMC) is described. The IMC includes a first circuit that includes a first plurality of tuning elements defined along a path. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The first circuit is coupled to an output. The IMC further includes a second circuit having a second plurality of tuning elements. The second circuit has an input coupled to a megahertz (MHz) RF generator and is coupled to the output. The IMC includes a uniformity control circuit (UCC) defined from at least one of the plurality of tuning elements of the first circuit. The UCC is connected serially along the path of the first circuit to define a capacitance that at least partially influences a radial uniformity profile in an etch rate produced by a plasma chamber.

Abstract: Systems and methods for controlling directionality of ion flux at an edge region within a plasma chamber are described. One of the systems includes a radio frequency (RF) generator that is configured to generate an RF signal, an impedance matching circuit coupled to the RF generator for receiving the RF signal to generate a modified RF signal, and a plasma chamber. The plasma chamber includes an edge ring and a coupling ring located below the edge ring and coupled to the first impedance matching circuit to receive the modified RF signal. The coupling ring includes an electrode that generates a capacitance between the electrode and the edge ring to control the directionality of the ion flux upon receiving the modified RF signal.

Abstract: An impedance matching circuit (IMC) is described. The IMC includes a first circuit that includes a first plurality of tuning elements defined along a path. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The first circuit is coupled to an output. The IMC further includes a second circuit having a second plurality of tuning elements. The second circuit has an input coupled to a megahertz (MHz) RF generator and is coupled to the output. The IMC includes a uniformity control circuit (UCC) defined from at least one of the plurality of tuning elements of the first circuit. The UCC is connected serially along the path of the first circuit to define a capacitance that at least partially influences a radial uniformity profile in an etch rate produced by a plasma chamber.

Abstract: An impedance matching circuit (IMC) is described. The impedance matching circuit includes a first circuit. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The IMC includes a second circuit. The second circuit has an input coupled to a low frequency megahertz (MHz) RF generator. The IMC includes a third circuit. The third circuit has an input coupled to a high frequency MHz RF generator. The IMC includes an output of the first, second, and third circuits coupled to an input of an RF transmission line. The first circuit and the second circuit provide isolation between a kHz RF signal sent through the first circuit and a low frequency MHz RF signal sent through the second circuit.

Abstract: An Electrostatic Chuck (ESC) in a chamber of a semiconductor manufacturing apparatus is presented for eliminating cooling-gas light-up. One wafer support includes a baseplate connected to a radiofrequency power source, a dielectric block, gas supply channels for cooling the wafer bottom, and first and second electrodes. The dielectric block is situated above the baseplate and supports the wafer when present. The first electrode is embedded in the top half of the dielectric block, where the top surface of the first electrode is substantially parallel to a top surface of the dielectric block, and the first electrode is connected to a DC power source. Further, the second electrode is embedded in a bottom half of the dielectric block, the second electrode being electrically connected to the first electrode, where the bottom surface of the second electrode is substantially parallel to a top surface of the baseplate.

Abstract: An impedance matching circuit (IMC) is described. The IMC includes a first circuit that includes a first plurality of tuning elements defined along a path. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The first circuit is coupled to an output. The IMC further includes a second circuit having a second plurality of tuning elements. The second circuit has an input coupled to a megahertz (MHz) RF generator and is coupled to the output. The IMC includes a uniformity control circuit (UCC) defined from at least one of the plurality of tuning elements of the first circuit. The UCC is connected serially along the path of the first circuit to define a capacitance that at least partially influences a radial uniformity profile in an etch rate produced by a plasma chamber.

Abstract: A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a radio frequency (RF) pulse signal. The RF pulse signal includes a first state and a second state. The first state has a higher power level than the second state. The method further includes receiving a pulse slope associated with the RF pulse signal. The pulse slope provides a transition between the first state and the second state. Also, the pulse slope is other than substantially infinite for reducing an amount of ion energy during the etch operation. The method includes determining power levels and timings for achieving the pulse slope and sending the power levels and the timings to an RF generator to generate the RF pulse signal.

Abstract: An impedance matching circuit (IMC) is described. The impedance matching circuit includes a first circuit. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The IMC includes a second circuit. The second circuit has an input coupled to a low frequency megahertz (MHz) RF generator. The IMC includes a third circuit. The third circuit has an input coupled to a high frequency MHz RF generator. The IMC includes an output of the first, second, and third circuits coupled to an input of an RF transmission line. The first circuit and the second circuit provide isolation between a kHz RF signal sent through the first circuit and a low frequency MHz RF signal sent through the second circuit.

Abstract: A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a radio frequency (RF) pulse signal. The RF pulse signal includes a first state and a second state. The first state has a higher power level than the second state. The method further includes receiving a pulse slope associated with the RF pulse signal. The pulse slope provides a transition between the first state and the second state. Also, the pulse slope is other than substantially infinite for reducing an amount of ion energy during the etch operation. The method includes determining power levels and timings for achieving the pulse slope and sending the power levels and the timings to an RF generator to generate the RF pulse signal.

Abstract: A plasma chamber is provided to increase conductance within the plasma chamber and to increase uniformity of the conductance. A radio frequency (RF) path for supplying power to the plasma chamber is symmetric with respect to a center axis of the plasma chamber. Moreover, pumps used to remove materials from the plasma chamber are located symmetric with respect to the center axis. The symmetric arrangements of the RF paths and the pumps facilitate an increase in conductance uniformity within the plasma chamber.

Abstract: An impedance matching circuit (IMC) is described. The impedance matching circuit includes a first circuit. The first circuit has an input coupled to a kilohertz (kHz) radio frequency (RF) generator. The IMC includes a second circuit. The second circuit has an input coupled to a low frequency megahertz (MHz) RF generator. The IMC includes a third circuit. The third circuit has an input coupled to a high frequency MHz RF generator. The IMC includes an output of the first, second, and third circuits coupled to an input of an RF transmission line. The first circuit and the second circuit provide isolation between a kHz RF signal sent through the first circuit and a low frequency MHz RF signal sent through the second circuit.

Abstract: A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a radio frequency (RF) pulse signal. The RF pulse signal includes a first state and a second state. The first state has a higher power level than the second state. The method further includes receiving a pulse slope associated with the RF pulse signal. The pulse slope provides a transition between the first state and the second state. Also, the pulse slope is other than substantially infinite for reducing an amount of ion energy during the etch operation. The method includes determining power levels and timings for achieving the pulse slope and sending the power levels and the timings to an RF generator to generate the RF pulse signal.

Abstract: A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes an electrode disposed within the processing chamber separate from the substrate support. The system also includes a power supply electrically connected to the electrode. The power supply is defined to supply electrical power to the electrode so as to liberate electrons from the electrode into the processing chamber.

Abstract: A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes an electron injection device for injecting electrons into the processing chamber to control an electron energy distribution within the processing chamber so as to in turn control an ion-to-radical density ratio within the processing chamber. In one embodiment, an electron beam source is defined to transmit an electron beam through the processing chamber above and across the substrate support.

Abstract: A top plate assembly is positioned above and spaced apart from the substrate support, such that a processing region exists between the top plate assembly and the substrate support. The top plate assembly includes a central plasma generation microchamber and a plurality of annular-shaped plasma generation microchambers positioned in a concentric manner about the central plasma generation microchamber. Adjacently positioned ones of the central and annular-shaped plasma generation microchambers are spaced apart from each other so as to form a number of axial exhaust vents therebetween. Each of the central and annular-shaped plasma generation microchambers is defined to generate a corresponding plasma therein and supply reactive constituents of its plasma to the processing region between the top plate assembly and the substrate support.

Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.

Abstract: A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled.

Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.