Patents by Inventor John Peter Stevenson

John Peter Stevenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-throughput BPF map manipulations with uprobes
    Patent number: 11928529
    Abstract: High-throughput BPF map manipulations with uprobes are disclosed. A method for manipulating a Berkeley Packet Filter (BPF) map comprises running a user program in a user space of a computing environment. The user program includes a trigger function. A corresponding kernel BPF probe is installed by the user program on the trigger function. The kernel BPF probe is triggered by reaching a memory address of the trigger function in the user space. The trigger function includes one or more arguments that the BPF map agent interprets as operation parameters. The BPF map agent performs one or more operations to manipulate a BPF map in the kernel space based on the operation parameters.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: March 12, 2024
    Assignee: NEW RELIC, INC.
    Inventors: Omid Jalal Azizi, John Peter Stevenson, Yaxiong Zhao
  • HIGH-THROUGHPUT BPF MAP MANIPULATIONS WITH UPROBES
    Publication number: 20230130274
    Abstract: High-throughput BPF map manipulations with uprobes are disclosed. A method for manipulating a Berkeley Packet Filter (BPF) map comprises running a user program in a user space of a computing environment. The user program includes a trigger function. A corresponding kernel BPF probe is installed by the user program on the trigger function. The kernel BPF probe is triggered by reaching a memory address of the trigger function in the user space. The trigger function includes one or more arguments that the BPF map agent interprets as operation parameters. The BPF map agent performs one or more operations to manipulate a BPF map in the kernel space based on the operation parameters.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Inventors: Omid Jalal Azizi, John Peter Stevenson, Yaxiong Zhao
  • Hardware-assisted paging mechanisms
    Patent number: 11392491
    Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Amin Firoozshahian, Omid Azizi, Chandan Egbert, David Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Alexandre Solomatnikov, John Peter Stevenson
  • HARDWARE-ASSISTED PAGING MECHANISMS
    Publication number: 20200004677
    Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Amin Firoozshahian, Omid Azizi, Chandan Egbert, David Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Alexandre Solomatnikov, John Peter Stevenson