Abstract: A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.

Abstract: A computer-implemented method, network switch and computer program product for performing exact match lookup operations in a table. A hash of the lookup key is performed to generate a value which is used to identify a location in the hash memory space. The generated value is separated into a bucket row, a bucket column, a bucket plane and a secondary hash value, where the bucket row, bucket column and bucket plane are used to identify an originating home hash root bucket. The head entry on the collision chain of a hash root bucket identified via the secondary hash value that is a neighbor to the home hash root bucket is read to determine if an exact match of the lookup key exists. If the head entry exactly matches the lookup key, then a finding of an exact match of the lookup key is reported.

Abstract: A mechanism is provided to maximize utilization of internal memory for packet queuing in network devices, while providing an effective use of both internal and external memory to achieve high performance, high buffering scalability, and minimizing power utilization. Embodiments initially store packet data received by the network device in queues supported by an internal memory. If internal memory utilization crosses a predetermined threshold, a background task performs memory reclamation by determining those queued packets that should be targeted for transfer to an external memory. Those selected queued packets are transferred to external memory and the internal memory is freed. Once the internal memory consumption drops below a threshold, the reclamation task stops.

Abstract: A mechanism is provided to maximize utilization of internal memory for packet queuing in network devices, while providing an effective use of both internal and external memory to achieve high performance, high buffering scalability, and minimizing power utilization. Embodiments initially store packet data received by the network device in queues supported by an internal memory. If internal memory utilization crosses a predetermined threshold, a background task performs memory reclamation by determining those queued packets that should be targeted for transfer to an external memory. Those selected queued packets are transferred to external memory and the internal memory is freed. Once the internal memory consumption drops below a threshold, the reclamation task stops.

Abstract: In an embodiment, a data storage and retrieval system includes a computing device that configures the computer memory according to an RTree (a type of logic tree) representing a structure of a spreadsheet. The computer memory may be internal to or external to the computing device. In an embodiment, the RTree has a plurality of nodes, at least some of which contain one or more minimum bounding rectangles. Each minimum bounding rectangle (“MBR”) encompasses cells of the spreadsheet from a different one of a plurality of columns of the spreadsheet, but does not encompass cells of any of the other columns of the plurality of columns. A node of the RTree may hold multiple MBRs or a single MBR.

Abstract: In an embodiment, a data storage and retrieval system includes a computing device that configures the computer memory according to an RTree (a type of logic tree) representing a structure of a spreadsheet. The computer memory may be internal to or external to the computing device. In an embodiment, the RTree has a plurality of nodes, at least some of which contain one or more minimum bounding rectangles. Each minimum bounding rectangle (“MBR”) encompasses cells of the spreadsheet from a different one of a plurality of columns of the spreadsheet, but does not encompass cells of any of the other columns of the plurality of columns. A node of the RTree may hold multiple MBRs or a single MBR.

Abstract: In an embodiment, a data storage and retrieval system includes a computing device that configures the computer memory according to an RTree (a type of logic tree) representing a structure of a spreadsheet. The computer memory may be internal to or external to the computing device. In an embodiment, the RTree has a plurality of nodes, at least some of which contain one or more minimum bounding rectangles. Each minimum bounding rectangle (“MBR”) encompasses cells of the spreadsheet from a different one of a plurality of columns of the spreadsheet, but does not encompass cells of any of the other columns of the plurality of columns. A node of the RTree may hold multiple MBRs or a single MBR.

Abstract: In an embodiment, a data storage and retrieval system includes a computing device that configures the computer memory according to an RTree (a type of logic tree) representing a structure of a spreadsheet. The computer memory may be internal to or external to the computing device. In an embodiment, the RTree has a plurality of nodes, at least some of which contain one or more minimum bounding rectangles. Each minimum bounding rectangle (“MBR”) encompasses cells of the spreadsheet from a different one of a plurality of columns of the spreadsheet, but does not encompass cells of any of the other columns of the plurality of columns. A node of the RTree may hold multiple MBRs or a single MBR.

Abstract: Methods and devices for scanning an incoming datastream for a plurality of target patterns. The scanning system receives an incoming data stream and stores the stream as sequential symbols in a register array. Previously received symbols are shifted in the array as incoming symbols are shifted in. A trigger stage computes a hash value based on the k most recently received symbols. The trigger stage then uses the hash value to determine whether a more detailed symbol by symbol comparison is required between a group of sequential symbols stored in the array and a target pattern stored in external storage. This is done by comparing the hash value with the indices of the target patterns in the external storage. If the more detailed comparison is indicated, a full comparison stage retrieves the relevant target pattern and compares the target pattern with the sequentially stored symbols in the array.

Abstract: Methods and systems for determining which groups of instructions are to be executed when a specific symbol patterns has been detected. A prefetch block receives an identification of the symbol pattern detected. The prefetch block then retrieves the groups of instructions which relate to that particular symbol pattern. These are passed to an execution block that retrieves state information for each user defined rule from which the groups of instructions originate. The execution block then checks, for each group of instructions, the state information. If the state information indicates that a particular group of instructions can be executed, the execution block executes that group.

Abstract: Methods and devices for scanning an incoming datastream for a plurality of target patterns. The scanning system receives an incoming data stream and stores the stream as sequential symbols in a register array. Previously received symbols are shifted in the array as incoming symbols are shifted in. A trigger stage computes a hash value based on the k most recently received symbols. The trigger stage then uses the hash value to determine whether a more detailed symbol by symbol comparison is required between a group of sequential symbols stored in the array and a target pattern stored in external storage. This is done by comparing the hash value with the indices of the target patterns in the external storage. If the more detailed comparison is indicated, a full comparison stage retrieves the relevant target pattern and compares the target pattern with the sequentially stored symbols in the array.

Abstract: Scheduler methods and apparatus utilize a weight limited FIFO (WLF) method to provide weighted per-connection queuing while maximizing preservation of cell arrival order, thus minimizing additional cell delay variation (CDV) added during scheduling. The invention minimizes additional CDV of a connection until the connection exceeds its fair share of resource utilization.

Abstract: Inter-class schedulers for digital link systems provide high efficiency utilization of limited bandwidth by employing queuing techniques referred to as Statistical Priority Guarantee Queuing (SPGQ) and Generic Cell-Rate Algorithm Priority Guarantee Queuing (GCRA-PGQ). SPGQ “elevates” the priority of otherwise low-priority classes under prescribed circumstances in accordance with a statistical process. The SPGQ scheduler determines whether a number within a range produced by a uniform random number generator lies within a sub-range proportional to the programmed statistical guarantee for a given class. If the number lies within the sub-range associated with a given class, then the priority of that class is elevated to a higher priority when both are eligible to transmit. The GCRA-PGQ scheduler operates as a strict priority mechanism until a class requires bandwidth in excess of a GCRA “window” or threshold for that class.

Abstract: In Asynchronous Transfer Mode (ATM) communications networks, certain congestion control features, such as Partial Packet Discard (PPD) and Early Packet Discard (EPD), operate on ATM cells that have been segmented from ATM Adaptation Layer #5 (AAL5) frames (packets). AAL5 frames are automatically detected by observing transitions of an indicator in the ATM cell header unique to AAL5 traffic. Automatic detection of AAL5 traffic allows enablement of packet discard techniques such as PPD and EPD.

Abstract: In Asynchronous Transfer Mode (ATM) communications networks, certain congestion control features, such as Partial Packet Discard (PPD) and Early Packet Discard (EPD), operate on ATM cells that have been segmented from ATM Adaptation Layer #5 (AAL5) frames (packets). AAL5 frames are automatically detected by observing transitions of an indicator in the ATM cell header unique to AAL5 traffic. Automatic detection of AAL5 traffic allows enablement of packet discard techniques such as PPD and EPD.

Abstract: Methods and systems consistent with the present invention store connection information in a memory of a node in a communications network such that the number of searches for retrieving the connection information is less than a predetermined probe threshold. The node includes a hash table and a connection table in the memory for storing and retrieving information associated with packets, frames, and/or cells in the communications network. Each entry in the hash table includes a connection identifier and, for example, a connection index, and is indexed according to a hash value based on the connection identifier. Each entry in the connection table includes connection state information that is indexed according to a connection index in the hash table. To store connection information in the memory, the node identifies in the hash table a first set of addresses that correspond to a first connection identifier.