Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: Methods and apparatus are provided for efficiently generating designs for testing design automation tools and applications. Randomized and diverse test designs with realistic attributes are automatically generated to allow comprehensive testing of design automation tools such as synthesis, simulation, and place and route tools used to implement designs on electronic devices. Each test design can incorporate a wide range of attributes to allow thorough integration testing of a design automation tool.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: A passive component integrated circuit chip formed on an insulative substrate includes a first conductive metallic layer on a major surface of the substrate; a layer of dielectric material on top of the first conductive metallic layer; a second conductive metallic layer on top of the formation of dielectric material; a layer of insulative material on top of the layer of dielectric material and on and around the second conductive metallic layer, but not completely covering the second conductive metallic layer; a conductive via in contact with a portion of the second conductive metallic layer left uncovered by the layer of insulative material; a resistive layer on top of the layer of insulative material and in contact with the conductive via; a conductive contact in contact with the resistive layer; and a passivation layer on top of the resistive layer so as to provide a seal between the resistive layer and the conductive contact.