Patents by Inventor John R. Cutter
John R. Cutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7843259Abstract: A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.Type: GrantFiled: July 18, 2005Date of Patent: November 30, 2010Assignee: NXP B.V.Inventor: John R. Cutter
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Publication number: 20090212846Abstract: A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.Type: ApplicationFiled: July 18, 2005Publication date: August 27, 2009Inventor: John R. Cutter
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Patent number: 7443648Abstract: A driver for an inductive load such as a solenoid coil 92 includes three FETs 4,6,8. Two of the FETs are reversely connected between battery and output terminals 16, 18, and one of the FETs is connected between output and ground terminals 16, 14. A driver circuit 10 having high and low side control circuitry 58,56 is formed in a common substrate with two of the FETs 4,6. In use, a coil 92 is connected to the output terminal 16, and driven in an energize mode in which current in the coil 92 is built up as indicated by arrow 100, a freewheel mode in which current circulates freely as indicated by arrow 102, and then may be switched off. The reversely connected FETs allow both short circuits to be prevented in the energize mode and allow the coil to be rapidly switched off. In spite of the control circuitry being formed in a common substrate with some of the FETs, the arrangement allows the FETs to be properly driven.Type: GrantFiled: April 8, 2004Date of Patent: October 28, 2008Assignee: NXP, B.V.Inventors: John R. Cutter, Brendan P. Kelly
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Patent number: 6724093Abstract: Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device.Type: GrantFiled: July 24, 2001Date of Patent: April 20, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: John R. Cutter
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Patent number: 6498071Abstract: In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11′) is provided in a trench (20) with a trench etchant mask (51, FIG. 2) still present so that the gate material (11′) forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, FIG. 5), and the gate (11) is then provided with an insulating overlayer (18, FIG. 6).Type: GrantFiled: November 29, 2000Date of Patent: December 24, 2002Assignee: Koninklijke Phillips Electronics N.V.Inventors: Erwin A. Hijzen, Cornelis E. Timmering, John R. Cutter
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Publication number: 20020008327Abstract: Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device.Type: ApplicationFiled: July 24, 2001Publication date: January 24, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventor: John R. Cutter
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Publication number: 20010009800Abstract: In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11′) is provided in a trench (20) with a trench etchant mask (51, FIG. 2) still present so that the gate material (11′) forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, FIG. 5), and the gate (11) is then provided with an insulating overlayer (18, FIG. 6).Type: ApplicationFiled: November 29, 2000Publication date: July 26, 2001Applicant: U.S. PHILIPS CORPORATIONInventors: Erwin A. Hijzen, Cornelis E. Timmering, John R. Cutter
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Patent number: 5864167Abstract: In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of operation of the device. A field plate structure (34, 34a, 34b, 34c) on an insulating layer (24) over the body portion (11) extends towards the outer periphery (14) to spread a depletion layer from the reverse-biased p-n junction (5) towards the outer periphery (14). The channel stopper (4) comprises concentrically doped stopper regions (41 to 44) with different doping concentrations and/or region widths and/or spacings, giving to the body portion (11) a non-uniform doping profile the doping of which, under the field plate structure (34, 34a, 34b, 34c), increases with distance (D) towards the outer periphery (14) to slow progressively the spread of the depletion layer under the field plate structure (34, 34a, 34b, 34c).Type: GrantFiled: January 16, 1998Date of Patent: January 26, 1999Assignee: U.S. Philips CorporationInventor: John R. Cutter