Abstract: This invention relates to the preparation of N-(phosphonomethyl)glycine (“glyphosate”) from N-(phosphonomethyl)iminodiacetic acid (“PMIDA”), and more particularly to methods for control of the conversion of PMIDA, for the identification of reaction end points relating to PMIDA conversion and the preparation of glyphosate products having controlled PMIDA content.

Abstract: A method and apparatus as described for predicting the performance of a computer system. A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. These are then converted into the corresponding sequence in the instruction set of the target. The performance of the target system in executing these instructions is then determined.

Abstract: A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

Abstract: Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

Abstract: In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

Abstract: A microprogrammed processor in which instructions have alternative fast and slow microprogram sequences. The fast sequences are designed for speed, and can detect exception conditions but do not resolve them. The slow sequences perform all the necessary tests to resolve these conditions. When a fast sequence detects an exception, that sequence is abandoned, and the corresponding slow sequence is run.

Abstract: A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address field. The address field addresses a control memory so as to read out a control word. Each control word specifies the way in which the control signals are mapped on to the control bits of the microinstruction. The output of the control memory controls switching logic which connects the control bits to the specified control signal lines. This variable mapping of the control signals allows the control signals to be packed into any available space in the microinstruction, thus reducing the required number of bits in the microinstruction without any significant loss of flexibility. Certain critical control signals however are derived from fixed positions in the microinstruction so as to avoid delays. These critical control signals are confirmed by validity signals from the control memory.

Abstract: A data processing system has a two-level storage system in which data items are copied from a main store into a smaller, faster slave store on demand. The mapping of the main store on to the slave store is a many-to-one mapping so that situations will occur where two required data items cannot both be present simultaneously in the slave store because they map on to the same location. The system has special logic which detects this situation and, upon detection, temporarily suspends the use of the slave store and instead uses a smaller first-in first-out area of storage.

Abstract: A pipelined data processing system having n processing stages, each of which is under the control of a central microprogram. Each microprogram instruction is decoded to produce n control signals, one for each processing stage. Microprogram start addresses are generated by combining information from the latest n program instructions received. Thus, each microprogram sequence implements a combination of phases of successive program instructions. A flag register is used to store relatively static control information, and effectively provides an extension of the microprogram instruction.