Abstract: A signature analyzer for testing digital circuits. The analyzer includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node.