Abstract: Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some embodiments, only the erase function is disabled in the device. Because programming data cannot then be erased from the device, the addition of new programming data is very unlikely to yield an operable design. Therefore, the programming function is also effectively disabled. The programming function can be directly disabled in addition to or instead of the erase function, if desired. The erase and/or programming functions can be disabled, for example, by blowing one or more fuses included in the erase and/or programming circuitry of the PLD.

Abstract: An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A plurality of intermediate stages are coupled to the first stage, where each intermediate stage receives an output from the immediate previous stage and an inverted output of each other previous intermediate stage, and generates a next most significant bit in a count. Finally, a last stage of the counter receives an inverted output of each previous intermediate stage except the immediate intermediate previous stage and generating a most significant bit in a count.

Abstract: Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some embodiments, only the erase function is disabled in the device. Because programming data cannot then be erased from the device, the addition of new programming data is very unlikely to yield an operable design. Therefore, the programming function is also effectively disabled. The programming function can be directly disabled in addition to or instead of the erase function, if desired. The erase and/or programming functions can be disabled, for example, by blowing one or more fuses included in the erase and/or programming circuitry of the PLD.

Abstract: Integrated circuits are disclosed that have interconnected programmable logic, and configuration memory. The interconnected programmable logic is connected by a logical interconnection network. The integrated circuits have a configurable function unit including a function unit component, such as a counter or shift register. The integrated circuits further include a configurable decoder, which decodes a value presented by the function unit component based on decoder configuration data. The integrated circuits also have at least one decoder output, which provides information about a comparison of the decoder configuration data with the value presented by the function unit component.

Abstract: An application specific processor for an application program is provided. First a software description, for example, a HDL description, of a processor is created. A user program is written using the processor's instruction set and compiled and/or assembled into object code. The software description of the processor and the object code are combined and synthesized into a logic gate circuit description, which may be implemented in a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD) or any other Integrated Circuit (IC) having programmable logic modules. Typically, the logic gate circuit description is optimized, hence reducing the number of logic gates and the resources needed.