Abstract: A computer system in which blocks of source code instructions are translated into blocks of target code instructions and executed. During execution, the system builds up dynamic behavior information about frequency of execution of, and relationships between, the blocks. On the basis of this information, a block coalition mechanism selects blocks, and combines them to form an optimized superblock of target code instructions that is functionally equivalent to the combination of the selected blocks. In this way, the system can start with relatively small, naively translated blocks, and build up larger, more optimized blocks, on the basis of the dynamic behavior of the code.

Abstract: A method of translating source code instructions into target code instructions is described. Prior to translate time, an existing interpreter is analyzed to identify sequences that implement individual source order code instructions. Sub-sequences within each template that implement predetermined sub-functions are identified and eliminated. The sequences are compiled and stored as templates. For each instruction in an input block of source code instructions, the appropriate template for that source code instruction is selected and appended to an output block of target code instructions. The source code block is then analyzed to determine the net effect of the non-implemented sub-functions, and code is planted in the output block to achieve this net effect.

Abstract: A data processing system comprises a number of processing nodes interconnected by a data transmission network. The network is "hairpin" shaped, having a first leg, a second leg, and a loopback connection connecting the first leg to the second leg. Each node sends public write messages on to the first leg, and receives messages from the second leg. All the messages flow through the loopback connection, which thus serves as a central chronology point for the system, defining a unique chronological order for the messages. The network can be reconfigured, to split it into a number of sub-networks, each with first and second legs interconnected by a loopback connection. The system may include a backup node, for disaster recovery, situated at a very long distance from the processing nodes.

Abstract: An apparatus for adding two BCD numbers, avoids the need for special adders with detection of carries between BCD digits. First, a sum without carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, without any carries between BCD digits. Next, a sum with carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, with carries between BCD digits. A mask pattern is then generated, comprising a six in each BCD digit where the sum without carries is unequal to the sum with carries. A result is then generated by forming the binary sum of the two numbers and the mask pattern, with carries between BCD digits.

Abstract: A data processing apparatus, having a visible register map for associating physical registers with logical registers. Instructions involving register-to-register transfers are executed by altering the association between the physical registers and the logical registers, without actually transferring data between the registers, so as to avoid logically redundant operations and to take such instructions out of the critical path of execution.

Abstract: In a microprogram unit, an index store is provided to translate index addresses, derived from input instructions, into start addresses for microprogram routines. Thus, if microprogram routines have to be re-ordered within the microprogram store, it is only necessary to modify the contents of the index store, and further modifications to the microprogram unit, or to the input instructions, are not necessary. Start addresses may be derived in an overlapped manner, so as to increase processing speed.