Abstract: A system for synchronized call forwarding of an incoming call from any of a plurality of telephones includes receiving a synchronized call forwarding command at a first telephony device, sending the synchronized call forwarding command from the first telephony device to a second telephony device over a first network, receiving a telephone call at the second telephony device over a second network, and forwarding the incoming call in accordance with the synchronized call forwarding command received from the first telephony device over the second network.

Abstract: In order for neural network technology to make useful determinations of the identity of letters and numbers that are processed in real time at a postal service sorting center, it is necessary for the neural network to "learn" to recognize accurately the many shapes and sizes in which each letter or number are formed on the address surface of the envelope by postal service users. It has been realized that accuracy in the recognition of many letters and numbers is not appreciably sacrificed if the neural network is instructed to identify those characteristics of each letter or number which are in the category "invariant." Then, rather than requiring the neural network to recognize all gradations of shape, location, size, etc. of the identified invariant characteristic, a generalized and bounded description of the invariant segments is used which requires far less inputting of sample data and less processing of information relating to an unknown letter or number.

Abstract: High-efficiency clock generator circuits having single or complementary outputs for driving capacitive loads. The clock generator has therein at least one pair of complementary FET switches, coupled between the output of the generator and power supply rails, and an inductor. The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract: An adiabatic dynamic non-inverter circuit is a mechanism by which a logic level signal and its inverse are simultaneously available in dynamic logic circuitry without significant power dissipation. The principles of this non-inverter circuit are used to create an exclusive-or gate which also does not dissipate significant power. Both of these circuits employ simplified circuit topologies.

Abstract: Power dissipation in precharge paths used in adiabatic dynamic logic circuitry is reduced by a precharge boost circuit which decreases the impedance between a clock node and an output node in such logic circuitry and thereby increases the charging current from a clock signal generator. In one example, a diode used to precharge an output node in adiabatic dynamic logic circuitry is selectively shorted by a controllable switch selectively connected in parallel with the diode when the output node is to be precharged.

Abstract: A method for improved thinning or skeletonizing handwritten characters or other variable-line-width images. The method scans a template set over the image to be thinned. Each template has a specific arrangement of dark and light pixels. At least one of those templates includes either more than three pixels per row or more than three rows of pixels. An odd number is good choice. Moreover, the templates are chosen so that each template can unconditionally delete image pixels without consideration of the effect of such deletions on the behavior of the other templates. Thus the templates are independent of each other.

Abstract: A time delay neural network is defined having feature detection layers which are constrained for extracting features and subsampling a sequence of feature vectors input to the particular feature detection layer. Output from the network for both digit and uppercase letters is provided by an output classification layer which is fully connected to the final feature detection layer. Each feature vector relates to coordinate information about the original character preserved in a temporal order together with additional information related to the original character at the particular coordinate point. Such additional information may include local geometric information, local pen information, and phantom stroke coordinate information relating to connecting segments between the end point of one stroke and the beginning point of another stroke.The network is also defined to increase the number of feature elements in each feature vector from one feature detection layer to the next.

Abstract: Highly accurate, reliable optical character recognition is afforded by a layered network having several layers of constrained feature detection wherein each layer of constrained feature detection includes a plurality of constrained feature maps and a corresponding plurality of feature reduction maps. Each feature reduction map is connected to only one constrained feature map in the same layer for undersampling that constrained feature map. Units in each constrained feature map of the first constrained feature detection layer respond as a function of a corresponding kernel and of different portions of the pixel image of the character captured in a receptive field associated with the unit.

Abstract: Highly accurate, reliable optical character recognition is afforded by a hierarchically layered network having several layers of parallel constrained feature detection for localized feature extraction followed by several fully connected layers for dimensionality reduction. Character classification is also performed in the ultimate fully connected layer. Each layer of parallel constrained feature detection comprises a plurality of constrained feature maps and a corresponding plurality of kernels wherein a predetermined kernel is directly related to a single constrained feature map. Undersampling is performed from layer to layer.

Abstract: Neural network type information processing devices have been proposed. In these devices, a matrix structure is utilized with impedance at the matrix intersection points. It has been found that excellent versatility in design is achieved by utilizing photoconductors at these intersection points and thus affording the possibility of controlling impedance by, in turn, controlling the level of incident light.

Abstract: A highly interconnected analog network is constructed with inter-neurons that account for energy function terms of order greater than two. The network comprises analog amplifiers that are connected with a resistive interconnection matrix which connects each amplifier output to the input of all other amplifiers. The connections embodied in the matrix are achieved with conductances whose values are computed in accordance with the set of problem restrictions, while the cost variables of the problem which are to be minimized are incorporated in the input signals.

Abstract: Advantageous neural network realizations are achieved by employing only negative gain amplifiers and a clipped T matrix having conductances T.sub.ij which have only two values. Preferably, one of these values is a preselected value set by the value of a fixed resistor, and the other value is zero, created simply with an open circuit. Values for the T.sub.ij terms of the clipped T matrix are obtained through an iterative process which operates on the clipped and nonclipped matrices and minimizes the error resulting from the use of the clipped T matrix.

Abstract: Superior performance is achieved by equalizing the time constants of amplifiers used in highly parallel computational networks. In accordance with one aspect of the invention a feedback arrangement is employed with the resistance between the input of each amplifier i and ground, and the capacitor between the input of each amplifier and ground are instead connected in parallel between the input of each amplifier and its corresponding output. In accordance with another aspect of the invention a balanced impedance arrangement is employed where, for example, a zero current with a non-zero thevenin conductance is achieved by employing equal valued T.sub.ij.sup.+ and T.sub.ij.sup.- conductances.