Abstract: A system for mask design repair may develop a simulation-based model of a layer thickness after one or more process steps for fabricating features on a sample, develop a transformed model of the fabrication process that emulates the simulation-based model and has a faster evaluation speed than the simulation-based model, and where the inputs to the transformed model include the input mask design, and where the outputs of the transformed model include one or more output parameters associated with fabrication of the input mask design as well as one or more sensitivity metrics describing sensitivities of the one or more output parameters to variations of the input mask design. The system may further receive a candidate mask design and generate a repaired mask design based on the transformed model and the candidate mask design.

Abstract: A system for mask design repair may develop a simulation-based model of a layer thickness after one or more process steps for fabricating features on a sample, develop a transformed model of the fabrication process that emulates the simulation-based model and has a faster evaluation speed than the simulation-based model, and where the inputs to the transformed model include the input mask design, and where the outputs of the transformed model include one or more output parameters associated with fabrication of the input mask design as well as one or more sensitivity metrics describing sensitivities of the one or more output parameters to variations of the input mask design. The system may further receive a candidate mask design and generate a repaired mask design based on the transformed model and the candidate mask design.

Abstract: A mask pattern for a semiconductor device can be used as an input to determine a photoresist thickness probability distribution using a machine learning module. For example, the machine learning module can determine a probability map of Z-height. This can be used to determine stochastic variation in photoresist thickness for a semiconductor device. The Z-height may be calculated at a coordinate in the X-direction and Y-direction.

Abstract: In some embodiments, a method may include improving a development process of a photoresist. The method may include simulating a negative-tone development process of a photoresist. The method may include determining a reaction of a developer with a soluble photoresist surface. Determining the reaction of the developer may include applying a reaction rate constant at a power of a reaction order to a blocked polymer concentration to yield a resist dissolution rate of soluble resist comprising the dissolution-limited regime of development. The method may include determining a flux of the developer into exposed and partially soluble resist. Determining the flux of the developer may include applying a vector valued diffusion coefficient of the developer dependent upon the blocked polymer concentration to a gradient of developer concentration to an expansion rate of insoluble resist comprising the expansion-controlled regime of development.

Abstract: In some embodiments, a method may include improving a development process of a photoresist. The method may include simulating a negative-tone development process of a photoresist. The method may include determining a reaction of a developer with a soluble photoresist surface. Determining the reaction of the developer may include applying a reaction rate constant at a power of a reaction order to a blocked polymer concentration to yield a resist dissolution rate of soluble resist comprising the dissolution-limited regime of development. The method may include determining a flux of the developer into exposed and partially soluble resist. Determining the flux of the developer may include applying a vector valued diffusion coefficient of the developer dependent upon the blocked polymer concentration to a gradient of developer concentration to an expansion rate of insoluble resist comprising the expansion-controlled regime of development.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile by determining a number acid generators and quenchers within a photoresist volume, determining a number of photons absorbed by the photoresist volume, determining a number of the acid generators converted to acid, determining a number of acid and quencher reactions within the photoresist volume, calculating a development of the photoresist volume, producing with the processor a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume, and measuring the dimensional properties of the photoresist profile.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile by determining a number acid generators and quenchers within a photoresist volume, determining a number of photons absorbed by the photoresist volume, determining a number of the acid generators converted to acid, determining a number of acid and quencher reactions within the photoresist volume, calculating a development of the photoresist volume, producing with the processor a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume, and measuring the dimensional properties of the photoresist profile.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile. A number acid generators and quenchers within a photoresist volume is determined. A number of photons absorbed by the photoresist volume is determined. A number of the acid generators converted to acid is determined. A number of acid and quencher reactions within the photoresist volume is determined. A development of the photoresist volume is calculated. The processor is used to produce a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume. The dimensional properties of the photoresist profile are measured.

Abstract: A method for setting processing parameters for fabricating an integrated circuit, by creating a mathematical model of a spin coated surface of a material over a non-flat substrate surface, where the mathematical model includes, a smoothing algorithm, where the smoothing algorithm uses as inputs only, a nominal thickness of the spin coated surface, a minimum thickness of the spin coated surface, and an interaction length, and a constraint that the spin coated surface cannot intersect the substrate surface, solving the mathematical model to determine the spin coated surface, and using the modeled spin coated surface to set the processing parameters for fabricating the integrated circuit.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile by determining a number acid generators and quenchers within a photoresist volume, determining a number of photons absorbed by the photoresist volume, determining a number of the acid generators converted to acid, determining a number of acid and quencher reactions within the photoresist volume, calculating a development of the photoresist volume, producing with the processor a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume, and measuring the dimensional properties of the photoresist profile.

Abstract: A method for setting processing parameters for fabricating an integrated circuit, by creating a mathematical model of a spin coated surface of a material over a non-flat substrate surface, where the mathematical model includes, a smoothing algorithm, where the smoothing algorithm uses as inputs only, a nominal thickness of the spin coated surface, a minimum thickness of the spin coated surface, and an interaction length, and a constraint that the spin coated surface cannot intersect the substrate surface, solving the mathematical model to determine the spin coated surface, and using the modeled spin coated surface to set the processing parameters for fabricating the integrated circuit.