Abstract: A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.

Abstract: A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.

Abstract: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.

Abstract: A method and system for detecting address generation interlock in a pipelined data processor is disclosed. The method comprises accumulating a plurality of vectors over a predefined number of processor clock cycles, with subsequent vectors corresponding to subsequent clock cycles; accumulating the status of one or more general registers in the plurality of vectors with the same bit location in each vector of the plurality of vectors corresponding to a particular general register; generating a list of pending general register updates from a logical combination of the plurality of vectors; and determining the existence of address generation interlock from the list of pending general register updates.

Abstract: An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is implemented via a pipe-lined computer processor executing a millicode routine. The processor interrogates a millicode condition code; interrogates a first field of the TMBP instruction, the results of which determine a logical function to be performed on the millicode condition code; interrogates a second field of the TMBP instruction which specifies a first millicode branch point; interrogates a third field of the TMBP instruction, which specifies a second millicode branch point; and sets a millicode condition code based upon the results of the interrogating and used for executing subsequent TMBP instructions or conditional branch instructions.

Abstract: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.

Abstract: A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.

Abstract: Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system.

Abstract: An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.

Abstract: An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.

Abstract: A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage.

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain mutliple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: In a data processing system which predecodes and queues a plurality of instructions for sequential presentation to an execution unit, and which includes a plurality of instruction-addressable general registers which can be utilized for temporary data storage or source of address modifying information, an interlock mechanism is provided to detect when an instruction is being decoded which requires use of a general register for address modification, but which register has not yet received new data by execution of an instruction awaiting execution in the queue of instructions. Two fields are associated with each instruction awaiting execution in the instruction queue. They identify one or more of the general registers to be loaded with data by execution of the instruction.

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

Abstract: Operand controls are provided in an I-unit using address operand pairs (AOPs), each pair consisting of a request register and a buffer register. When handling variable field length (VFL) instructions with source (SRC) and destination (DST) operand addresses, two AOPs are generally assigned to receive different parts of the first subline (e.g. doubleword) of the SRC operand; this is called a duplicate fetch and is used with any size VFL operand. Efficiency is improved for the special case in which the DST operand has all of its bytes confined to a single subline in main storage by detecting the special case and inhibiting a duplicate fetch signal to the I-unit controls which assign duplicate AOPs to an instruction. The SRC operand may have more than one subline but the alignment controls force all source operand bytes into a single subline for the special case. When the duplicate fetch signal is suppressed, only one AOP is assigned by the controls to the first subline fetch for the SRC operand.

Abstract: Operand controls are provided in an I-unit which includes a plurality of address operand pairs (AOP's). Each AOP has an operand request register and an operand buffer. The AOP's are used to fetch the subline (e.g. doubleword) of operands in variable length field (VLF) instructions (such as LM, MVC, CLC, XC, etc.). Each AOP is capable of requesting and receiving a single subline fetched by a storage control. Each AOP buffers its received subline until needed for executing the instruction. The bytes of VLF operands are not aligned on subline boundaries. The AOP's are dynamically selected to fetch the sublines of current operand(s). The AOP's selected for a single operand are sequenced by a chain of back pointers held in latches, which respectively represent the AOP's. Each latch receives the identifier (ID) of the previous AOP in the chain for the operand. An associative search through the previous ID's in all latches obtains the forward order of AOP ID's.

Abstract: In the case of a cache miss, the successive fetch requests by the I-unit for sublines (e.g. doublewords) of a variable length field operand are provided by the first through the highest-address fetched sublines in a line being accessed from main storage via a cache bypass. This avoids the time delay for the I-unit caused by waiting until the complete line has been transferred to the cache before all required sublines in the line are obtainable from the cache. Address operand pairs (AOP's) consisting of request and buffer registers are provided in the I-unit to handle the fetched sublines as fast as the cache bypass can provide them from main storage. If there is a cache hit, the sublines are accessed from the cache.