Patents by Inventor John S. Mangan
John S. Mangan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080192546Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: ApplicationFiled: April 2, 2008Publication date: August 14, 2008Inventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 7362613Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: February 26, 2007Date of Patent: April 22, 2008Assignee: Sandisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 7246268Abstract: Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors includes updating a counter, comparing the counter to a threshold value, and generating an appropriate indication when comparing the counter to the threshold value yields a first result. The counter is updated each time a sector is reassigned, and indicates a number of sectors remaining in the memory system. The threshold value indicates a number of sectors which are yet to be reassigned in order for the memory system to be considered as useable, or reliable. The indication is generated when comparing the counter to the threshold value yields a first result to indicate that the memory system is substantially near a failure condition.Type: GrantFiled: January 16, 2002Date of Patent: July 17, 2007Assignee: SanDisk CorporationInventors: Jeffrey Craig, John S. Mangan
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Patent number: 7184306Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: December 29, 2005Date of Patent: February 27, 2007Assignee: SanDisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6996008Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: May 6, 2004Date of Patent: February 7, 2006Assignee: SanDisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6888752Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: July 1, 2003Date of Patent: May 3, 2005Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Publication number: 20040237010Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.Type: ApplicationFiled: June 22, 2004Publication date: November 25, 2004Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
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Publication number: 20040210709Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: ApplicationFiled: May 6, 2004Publication date: October 21, 2004Inventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6760255Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: April 23, 2003Date of Patent: July 6, 2004Assignee: SanDisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6717851Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: January 10, 2001Date of Patent: April 6, 2004Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Publication number: 20040027865Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: ApplicationFiled: July 1, 2003Publication date: February 12, 2004Inventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Publication number: 20030206441Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: ApplicationFiled: April 23, 2003Publication date: November 6, 2003Inventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Publication number: 20030135793Abstract: Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors includes updating a counter, comparing the counter to a threshold value, and generating an appropriate indication when comparing the counter to the threshold value yields a first result. The counter is updated each time a sector is reassigned, and indicates a number of sectors remaining in the memory system. The threshold value indicates a number of sectors which are yet to be reassigned in order for the memory system to be considered as useable, or reliable. The indication is generated when comparing the counter to the threshold value yields a first result to indicate that the memory system is substantially near a failure condition.Type: ApplicationFiled: January 16, 2002Publication date: July 17, 2003Applicant: SanDisk CorporationInventors: Jeffrey Craig, John S. Mangan
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Patent number: 6580638Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: June 21, 2002Date of Patent: June 17, 2003Assignee: SanDisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6570785Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: October 31, 2000Date of Patent: May 27, 2003Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang
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Publication number: 20020154543Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: ApplicationFiled: June 21, 2002Publication date: October 24, 2002Inventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Patent number: 6426893Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.Type: GrantFiled: February 17, 2000Date of Patent: July 30, 2002Assignee: Sandisk CorporationInventors: Kevin M. Conley, John S. Mangan, Jeffrey G. Craig
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Publication number: 20020051383Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: ApplicationFiled: January 10, 2001Publication date: May 2, 2002Inventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Patent number: 6049899Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.Type: GrantFiled: July 8, 1998Date of Patent: April 11, 2000Assignee: Zilog, Inc.Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
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Patent number: 5657332Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.Type: GrantFiled: March 20, 1995Date of Patent: August 12, 1997Assignee: SanDisk CorporationInventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra