Abstract: A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.

Abstract: A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.

Abstract: A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines.