Patents by Inventor John S. Yates
John S. Yates has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6978462Abstract: A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.Type: GrantFiled: June 11, 1999Date of Patent: December 20, 2005Assignee: ATI International SRLInventors: Michael C. Adler, John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Stephen C. Purcell
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Patent number: 6954923Abstract: An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.Type: GrantFiled: July 7, 1999Date of Patent: October 11, 2005Assignee: ATI International SRLInventors: John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke
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Patent number: 6941545Abstract: A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.Type: GrantFiled: May 28, 1999Date of Patent: September 6, 2005Assignee: ATI International SRLInventors: David L. Reese, John S. Yates, Jr., Paul H. Hohensee, Korbin S. Van Dyke, T. R. Ramesh, Shalesh Thusoo, Gurjeet Singh Saund, Niteen Aravind Patkar
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Patent number: 6826748Abstract: A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.Type: GrantFiled: June 24, 1999Date of Patent: November 30, 2004Assignee: ATI International SRLInventors: Paul H. Hohensee, David L. Reese, John S. Yates, Jr., Korbin S. Van Dyke, T. R. Ramesh, Shalesh Thusoo, Gurjeet Singh Saund, Niteen Aravind Patkar
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Patent number: 6789181Abstract: A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.Type: GrantFiled: November 3, 1999Date of Patent: September 7, 2004Assignee: ATI International, SRLInventors: John S. Yates, David L. Reese, Korbin S. Van Dyke, Paul H. Hohensee
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Patent number: 6779107Abstract: A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class.Type: GrantFiled: October 28, 1999Date of Patent: August 17, 2004Assignee: ATI International SRLInventor: John S. Yates
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Patent number: 6763452Abstract: A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events.Type: GrantFiled: June 24, 1999Date of Patent: July 13, 2004Assignee: ATI International SRLInventors: Paul H. Hohensee, John S. Yates, Jr., Korbin S. Van Dyke, David L. Reese, Stephen C. Purcell
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Patent number: 6549959Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory.Type: GrantFiled: November 4, 1999Date of Patent: April 15, 2003Assignee: ATI International SrlInventors: John S. Yates, David L. Reese, Korbin S. Van Dyke
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Patent number: 6535903Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: March 18, 2003Assignee: Compaq Information Technologies Group, L.P.Inventors: John S. Yates, Steven Tony Tye
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Patent number: 6502237Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: February 11, 2000Date of Patent: December 31, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: John S. Yates, Steven Tony Tye, Raymond J. Hookway
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Patent number: 6397379Abstract: A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.Type: GrantFiled: October 28, 1999Date of Patent: May 28, 2002Assignee: ATI International SRLInventors: John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke
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Apparatus and a method for variable size pages using fixed size translation lookaside buffer entries
Patent number: 6374341Abstract: The present invention provides an apparatus and a method for variable size pages using fixed size TLB (Translation Lookaside Buffer) entries. In one embodiment, an apparatus for variable size pages using fixed size TLB entries includes a first TLB for fixed size pages and a second TLB for variable size pages. In particular, the second TLB stores fixed size TLB entries for variable size pages. Further, in one embodiment, an input of an OR device is connected to the second TLB to provide a cost-effective and efficient implementation for translating linear addresses to physical addresses using fixed size TLB entries stored in the second TLB.Type: GrantFiled: September 2, 1998Date of Patent: April 16, 2002Assignee: ATI International SRLInventors: Sandeep Nijhawan, Denis Gulsen, John S. Yates, Jr. -
Publication number: 20020032718Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: ApplicationFiled: January 29, 1996Publication date: March 14, 2002Inventors: JOHN S. YATES, STEVEN T. TYE
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Patent number: 6226789Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: May 1, 2001Assignee: Compaq Computer CorporationInventors: Steven Tony Tye, John S. Yates
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Patent number: 6091897Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: July 18, 2000Assignee: Digital Equipment CorporationInventors: John S. Yates, Scott G. Robinson, Mark Herdeg
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Patent number: 6000028Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: December 7, 1999Assignee: Digital Equipment CorporationInventors: Anton Chernoff, John S. Yates
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Patent number: 5930509Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: July 27, 1999Assignee: Digital Equipment CorporationInventors: John S. Yates, Steven Tony Tye, Raymond J. Hookway
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Patent number: 5842017Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: November 24, 1998Assignee: Digital Equipment CorporationInventors: Raymond J. Hookway, John S. Yates, Steven Tony Tye
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Patent number: 5802373Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.Type: GrantFiled: January 29, 1996Date of Patent: September 1, 1998Assignee: Digital Equipment CorporationInventors: John S. Yates, Stephen C. Root
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Patent number: 5051885Abstract: Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit.Type: GrantFiled: October 7, 1988Date of Patent: September 24, 1991Assignee: Hewlett-Packard CompanyInventors: John S. Yates, Jr., Stephen J. Ciavaglia, John Manton, Michael Kahaiyan, Richard G. Bahr, Barry J. Flahive