Abstract: A digital processor system includes a processor, a memory and a memory interface between the processor and the memory. The memory stores data in one bit format but addresses the data in a second bit format. The interface to the memory includes a controller that is responsive to the processor, an information bus for the transfer of addresses and data and two registers to store addresses for the memory. These registers in the interface are responsive to the processor through the interface controls in order to allow the processor to increment or decrement the memory addresses or load new memory addresses from the information bus. These registers are then connected to a switch which is in turn responsive to the processor through the interface control in order that the processor can determine which register is to provide the address to the memory.

Abstract: A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.

Abstract: A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.