Patents by Inventor John Smolka

John Smolka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory register having an integrated delay-locked loop
    Patent number: 8151132
    Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: April 3, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventor: John Smolka
  • Buffered DRAM
    Patent number: 8094504
    Abstract: A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: January 10, 2012
    Assignee: Integrated Device Technology inc.
    Inventor: John Smolka
  • MEMORY REGISTER HAVING AN INTEGRATED DELAY-LOCKED LOOP
    Publication number: 20100042863
    Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventor: JOHN SMOLKA
  • Buffered DRAM
    Publication number: 20090175090
    Abstract: A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 9, 2009
    Inventor: John Smolka