Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

Abstract: An aperture in an electronic substrate is filled with a filling material without need for a specially built fill mask. A layer of tape or tentable photosensitive dielectric film is applied to one surface of the substrate covering the aperture. An opening is made in the tape or film by directing radiation through the aperture. Fill material is then forced through the opening to substantially fill the aperture. Protruding nubs may be removed to planarize the substrate surfaces.

Abstract: Pads which are attached to a high density printed circuit board (PCB) having a plurality of through-holes opening on the top surface. A plurality of pads are formed on a carrier sheet so that each of the pads have a copper layer proximate to the carrier sheet and a joining metal layer formed on top of said copper layer. The plurality of pads are positioned on the carrier sheet so that they are aligned with the through-hole pattern on the top surface of the PCB, the pads bing laminated to the through-holes on the top surface using the joining metal, and the carrier sheet being separated from the plurality of pads that are joined to the through-holes so that the copper layer is exposed. The pads may possess a variety of shapes such as disk-shaped, elongated, or rectangular, and can cover one or multiple through-holes. An electrical component may be soldered to the pad.

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

Abstract: A method for attaching pads to a high density printed circuit board (PCB) having a plurality of through-holes opening on the top surface. The method includes forming a plurality of pads on a carrier sheet so that each of said pads have a copper layer proximate to said carrier sheet and a joining metal layer formed on top of said copper layer, positioning the plurality of pads on the carrier sheet so that they are aligned with the through-hole pattern on the top surface of the PCB, laminating the pads to the through-holes on the top surface using the joining metal, and separating the carrier sheet from the plurality of pads that are joined to the through-holes so that the copper layer is exposed. The pads may comprise a variety of shapes such as disk-shaped, elongated, or rectangular, and can cover one or multiple through-holes. An electrical component may be soldered to the pad.

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 3.5% The invention also relates to methods of making the dielectric coated chip carrier.

Abstract: A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads.

Abstract: A novel through-hole interconnect for connecting a power plane conductor to a through-hole includes a central pad connected to the through-hole and a deformable hinge that connects the central pad with the power plane conductor in a multilayer circuit board. The central pad and hinge are defined by a non-continuous area removed from the plane conductor. Preferably this area has a C-shape. During the compression process to join the core assemblies, deformation of the hinge advantageously absorbs the shear forces and allows the power plane beyond the hinge to remain substantially planar. The resulting multilayer laminated circuit board includes a plurality of cores laminated together in a stacked configuration and a plurality of plated through-holes defined in said multilayer laminated circuit board each of which is connected to a plane conductor by a hinge deformed so that the interconnect area is aligned outside of a plane defined by the plane conductor.