Patents by Inventor John T. Petersen

John T. Petersen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High reliability triple redundant latch with integrated testability
    Patent number: 7095262
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: August 22, 2006
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: John T. Petersen, Hassan Naser, Jonathan P Lotz
  • Soft-error rate improvement in a latch
    Patent number: 7068088
    Abstract: In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first inverter. When the input to the first inverter is disturbed by a soft error event, a signal tristates the first inverter.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: June 27, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: John T. Petersen
  • High reliability triple redundant memory element with integrated testability and voting structures on each latch
    Patent number: 7027333
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: April 11, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John T. Petersen, Hassan Naser, Jonathan P Lotz