Abstract: A computing system includes a storage server having a memory organization that includes a compressed memory device for storing sectors, each sector having a sector data portion and associated header and trailers, either attached by the hosts or by components of the computing system. The compressed memory device comprises a memory directory and a plurality of fixed-size blocks. The system implements a methodology for detaching headers and trailers from sectors before storing the sectors in the memory, and storing the headers and trailers in the memory disk cache, separate from the sector data portion; and, reattaching headers and trailers to sector data portions when the sectors are sent from the memory to a host or to a mass storage device. The header and trailer data are managed through the same memory directory used to manage the compressed main memory.

Abstract: The invention is a method of measuring transfer functions of a physical system using a wideband excitation signal by exciting the system with a low-power, wide band input signal that has a rich frequency content over a wide band and using a stochastic process to derive a system transfer function over the excitation signal bandwidth.

Abstract: A computing system includes a storage server having a memory organization that includes a compressed memory device for storing sectors, each sector having a sector data portion and associated header and trailers, either attached by the hosts or by components of the computing system. The compressed memory device comprises a memory directory and a plurality of fixed-size blocks. The system implements a methodology for detaching headers and trailers from sectors before storing the sectors in the memory, and storing the headers and trailers in the memory disk cache, separate from the sector data portion; and, reattaching headers and trailers to sector data portions when the sectors are sent from the memory to a host or to a mass storage device. The header and trailer data are managed through the same memory directory used to manage the compressed main memory.

Abstract: A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.

Abstract: System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The method includes steps of providing common memory area in main memory for storing compressed and uncompressed data segments; accessing directory structure formed in the main memory having entries for locating both uncompressed data segments and compressed data segments for cache miss operations, each directory entry including index for locating data segments in the main memory and further indicating status of the data segment; and, checking a status indication of a data segment to be accessed for a cache miss operation, and processing either a compressed or uncompressed data segment from the common memory area according to the status.

Abstract: A system for accessing contents of the directory structure in a computing system having a CPU and implementing indirectly addressable main memory via a first directory structure included in the memory. In this system, CPU generated real memory addresses are translated to one or more physical memory locations using the directory structure. A second directory structure is provided in main memory that includes one or more entries with each entry formatted to provide addressability to a predetermined number of entries in the first directory structure. The second directory structure alternately may access all contents of main memory, and is adaptable as main memory capacity varies. The second directory structure may alternately be implemented as a hardware device which computes the addresses for accessing data in main memory.

Abstract: A system for accessing contents of the directory structure in a computing system having a CPU and implementing indirectly addressable main memory via a first directory structure included in the memory. In this system, CPU generated real memory addresses are translated to one or more physical memory locations using the directory structure. A second directory structure is provided in main memory that includes one or more entries with each entry formatted to provide addressability to a predetermined number of entries in the first directory structure. The second directory structure alternately may access all contents of main memory, and is adaptable as main memory capacity varies. The second directory structure may alternately be implemented as a hardware device which computes the addresses for accessing data in main memory.

Abstract: A system for writing data to a disk array includes a cache memory coupled to the disk array for storing data indicative of locations on the disk array and parity blocks associated with parity groups including the locations. Each of the parity blocks includes an identifier indicative of locations within a particular parity group which are protected by the parity data. Write logic reads the identifier from the parity block, and based thereon, determines whether a disk location is not protected by the parity data. The write logic also writes to the location and updates the parity data and the identifier associated with the parity block to include the location of the data block to indicate that the location is protected.

Abstract: A wait depth limited concurrency control method for use in a multi-user data processing environment restricts the depth of the waiting tree to a predetermined depth, taking into account the progress made by transactions in conflict resolution. In the preferred embodiment for a centralized transaction processing system, the waiting depth is limited to one. Transaction specific information represented by a real-valued function L, where for each transaction T in the system at any instant in time L(T) provides a measure of the current "length" of the transaction, is used to determine which transaction is to be restarted in case of a conflict between transactions resulting in a wait depth exceeding the predetermined depth. L(T) may be the number of locks currently held by a transaction T, the maximum of the number of locks held by any incarnation of transaction T, including the current one, or the sum of the number of locks held by each incarnation of transaction T up to the current one.

Abstract: A cache directory keeps track of which blocks are in the cache, the number of times each block in the cache has been referenced after aging at least a predetermined amount (reference count), and the age of each block since the last reference to that block, for use in determining which of the cache blocks is replaced when there is a cache miss. At least one preselected age boundary threshold is utilized to determine when to adjust the reference count for a given block on a cache hit and to select a cache block for replacement as a function of reference count value and block age.

Abstract: The transition table size and table-driven locking facilities if reduced by decomposing lock states into canonical states and canonical-actual maps, mapping actual processors to canonical processors, looking up a transition in a table which contains a new canonical state, notify bits and a canonical-canonical map, permuting the canonical-actual map using the canonical-canonical map, and permuting the notify bits using the original canonical-actual map.

Abstract: In order to produce wafers suitable for fabrication of integrated circuits, an ingot of raw silicon must undergo a process which includes several steps. The ingot must be sawed into slices, the slices edge ground to remove roughness of the edges, lapped to remove as much saw damage as possible, stress relief etched to remove as small a damaged area as possible, then polished. Each of these steps requires removal of some of the material of the slice. The use of laser annealing reduces the amount of surface removed, as it repairs some surface damage, smoothes the surface, and when accomplished in a partial vacuum, improves the chemical composition of the material as related to electrical activity.