Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification.

Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. If the command is to initiate the retrieval of information from the other element, the other element stores the command and address information in a storage file. The storage file can accumulate a number of commands and related addresses thereby to allow the different commanding nexuses to initiate similar transfers from a single one of the other elements without producing a busy indication.

Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification.

Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.

Abstract: A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle.

Abstract: A secondary storage facility for a data processing system including a drive unit which connects to a pair of controllers. Switching circuits in the drive unit couple a data transfer section and a common control section for the transfer section to one or the other controller in response to selection signals. Other control sections connect to respective ones of the controllers to receive signals and a selection circuit responds by transmitting the selection signals. If one controller tries to transfer information to or from the common control section while the selection signal designates the other controller, the transfer does not occur. If the attempted transfer is to the common control section or from predetermined locations in the common control section, the attempt is retained so the drive can signal back through the other controller when the selection signal can change. If the attempted transfer is from the common control section, then the drive transmits back to the controller a unique code.

Abstract: A secondary storage facility including magnetic tape, disk or drum units or other sequential access storage units. Each storage unit or drive connects to a controller by means of a device bus with asynchronous and synchronous paths. Status and controller information is coupled between the controller and a selected drive unit asynchronously over the asynchronous bus. Actual data transfers occur between the controller and a drive over the synchronous bus and between other units in the system and the controller using direct memory access or equivalent data transfers.