Abstract: An architecture component for use in performing a wavelet transform of a sampled signal, and an architecture including such components are disclosed. The architecture component includes a multiplier, and a multiplexor to multiplex a number n of filter coefficients onto the multiplier. The multiplier processes n consecutive samples with consecutive coefficients, successive multiplier outputs being stored for subsequent processing to generate an output of the filter after every n samples. The wavelet transform may be a discrete wavelet transform or a wavelet packet decomposition. The architecture component may be configured to multiplex two or more coefficients onto a multiplier. Embodiments are disclosed in which the components are derived from a parameterized description in a hardware description language.

Abstract: One aspect of the invention provides an apparatus for selectably encrypting or decrypting data, the apparatus being arranged to receive a control signal for selecting between encryption and decryption. The apparatus comprises at least one data processing module arranged to perform one or more data encryption or data decryption operations depending on the setting of said control signal, wherein at least part of said data processing module comprises one or more programmable Look-up Tables (LUTs). The apparatus further comprises at least one storage device for storing a first set and a second set of LUT values, the apparatus being arranged to program some or all of said LUTs with said first set of LUT values when said control signal is set to encrypt, and to program some or all of said LUTs with said second set of LUT values when said control signal is set to decrypt. In the preferred embodiment, the apparatus is arranged to implement the Advanced Encryption Standard, or Rijndael, cipher.

Abstract: Architecture and method for performing discrete wavelet transforms An architecture component an a method for use in performing a 2-dimensional discrete wavelet transform of 2-dimensional input data is disclosed. The architecture component comprises a serial processor for receiving the input signal row-by-row, a memory for receiving output coefficients from the serial processor, and a parallel processor for processing coefficients stored in the memory and a serial processor for processing further octaves. The parallel processor is operative to process in parallel coefficients previously derived from one row of input data by the serial processor.

Abstract: One aspect of the invention provides a computer useable product co-operable with a circuit synthesis tool for generating a data encryption and apparatus for encrypting a block of plaintext data using a cipher key to produce a block of encrypted data. The product provides a first parameter, programmable by a user, the value of which determines the length of the cipher key. The product is arranged to cause the apparatus to implement a number of encryption rounds, the number of rounds depending on the value of the first parameter. The computer useable product further includes means for implementing a key schedule module for generating, from the cipher key, a number of round keys for use in respective encryption rounds, the number of generated round keys depending on the value of the first parameter. The product preferably takes the form of one or more blocks of HDL (Hardware Description Language) code.

Abstract: An architecture component for use in performing a wavelet transform of a sampled signal, and an architecture including such components are disclosed. The architecture component includes a multiplier, and a multiplexor to multiplex a number n of filter coefficients onto the multiplier. The multiplier processes n consecutive samples with consecutive coefficients, successive multiplier outputs being stored for subsequent processing to generate an output of the filter after every n samples. The wavelet transform may be a discrete wavelet transform or a wavelet packet decomposition. The architecture component may be configured to multiplex two or more coefficients onto a multiplier. Embodiments are disclosed in which the components are derived from a parameterized description in a hardware description language.

Abstract: A data encryption or decryption apparatus for encrypting or decrypting blocks of data. The apparatus includes a data processing pipeline having at least two pipelined data processing modules each arranged to perform an encryption or decryption operation, in conjunction with a respective sub-key. The apparatus further includes a sub-key generating module for generating a respective sub-key for each data processing module and a sub-key skewing module arranged to provide each sub-key to its respective data processing module. The arrangement is such that the sub-key skewing module synchronises the provision of each sub-key to its respective data processing module with the passage of a data block through the data processing pipeline so that the data block is encrypted or decrypted using sub-keys generated from a common primary key. The apparatus is particularly suitable for use in the implementation of the Data Encryption Standard (DES).

Abstract: A commutator circuit has a plurality of stages connected in series, each stage having a plurality of data inputs and a like plurality of data outputs with the data outputs of each stage being connected in one-to-one correspondence to the data inputs of the next stage. Each stage includes a plurality of data transposition circuits each connected between a respective pair of the data inputs and a respective pair of the data outputs for that stage. Each data transposition circuit includes two 2-to-1 selector switches each having two inputs connected to respective ones of the pair of data inputs and a single output connected to a respective one of the pair of data outputs, a first delay element connected between one of the data inputs and the two selector switches, and a second delay element connected to the output of one of the selector switches.