Abstract: Systems and methods used for bilinear texture filtering may also be used to perform font filtering. Font data stored as a texture is read from memory in blocks that are coarsely aligned. Font alignment units may be used to provide a finely aligned region of the font data within a font filter footprint. The finely aligned region is then filtered using bilinear filtering to produce font coverage information representing a grayscale value for a pixel. Using existing bilinear filtering engines in conjunction with font alignment and sample units reduces the need for having a specific engine to perform each of the font filtering operations, possibly saving die area in a graphics system.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: Systems and methods for processing linear colorspace data may be reused to process nonlinear colorspace data at a comparable performance level while maintaining the precision of the nonlinear colorspace data. Nonlinear colorspace data is converted to a compact floating point format in a linear colorspace used by conventional graphics processors. The compact floating point format includes an 8 bit explicit mantissa (without an implied leading one) and a 3 bit exponent to maintain the precision of the nonlinear colorspace data. The 8 bit mantissa may be processed by conventional texture filtering units designed to process 8 bit (fixed or floating point) color values. The 3 bit exponent may by processed by conventional texture filtering units designed to process floating point color values.

Abstract: Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock.