Patents by Inventor John W. Brothers

John W. Brothers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9589366
    Abstract: Graphics processing is performed in which a decision is made in individual tiles whether or not to sample at a reduced sampling rate. A sampling pattern is selected from a set of sampling patterns having the same reduced sampling rate. The sampling pattern is dithered over a set of frames to reduce the visual appearance of visual artifacts via temporal color averaging.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhinav Golas, Karthik Ramani, John W. Brothers
  • Patent number: 9589367
    Abstract: A graphics system includes a reconstruction unit that utilizes higher order polynomials, such as cubic splines, to reconstruct missing pixel data. The computational work to perform interpolation with higher order polynomials, such as cubic splines, is reduced by pre-calculating weights for each sparse sample pattern. The pre-calculated weights may be stored as stencils and used during runtime to perform interpolation.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhinav Golas, Karthik Ramani, John W. Brothers
  • Publication number: 20170011288
    Abstract: Implementing a neural network can include receiving a macro instruction for implementing the neural network within a control unit of a neural network processor. The macro instruction can indicate a first data set, a second data set, a macro operation for the neural network, and a mode of operation for performing the macro operation. The macro operation can be automatically initiated using a processing unit of the neural network processor by applying the second data set to the first data set based on the mode of operation.
    Type: Application
    Filed: June 27, 2016
    Publication date: January 12, 2017
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160371857
    Abstract: Image processing may include separating a noise component from an original image resulting in a de-noised image and determining a noise parameterization for the noise component. The de-noised image and the noise parameterization may be compressed.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventor: John W. Brothers
  • Publication number: 20160364644
    Abstract: A spiking neural network having a plurality layers partitioned into a plurality of frustums using a first partitioning may be implemented, where each frustum includes one tile of each partitioned layer of the spiking neural network. A first tile of a first layer of the spiking neural network may be read. Using a processor, a first tile of a second layer of the spiking neural network may be generated using the first tile of the first layer while storing intermediate data within an internal memory of the processor. The first tile of the first layer and the first tile of the second layer belong to a same frustum.
    Type: Application
    Filed: March 7, 2016
    Publication date: December 15, 2016
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160358307
    Abstract: A graphics system interleaves a combination of graphics renderer operations and compute shader operations. A set of API calls is analyzed to determine dependencies and identify candidates for interleaving. A compute shader is adapted to have a tiled access pattern. The interleaving is scheduled to reduce a requirement to access an external memory to perform reads and writes of intermediate data.
    Type: Application
    Filed: December 28, 2015
    Publication date: December 8, 2016
    Inventors: John W. BROTHERS, Joohoon LEE, Abhinav GOLAS
  • Publication number: 20160358069
    Abstract: Implementing a neural network includes determining whether to process a combination of a first region of an input feature map and a first region of a convolution kernel and, responsive to determining to process the combination, performing a convolution operation on the first region of the input feature map using the first region of the convolution kernel to generate at least a portion of an output feature map.
    Type: Application
    Filed: April 14, 2016
    Publication date: December 8, 2016
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160358070
    Abstract: Tuning a neural network may include selecting a portion of a first neural network for modification to increase computational efficiency and generating, using a processor, a second neural network based upon the first neural network by modifying the selected portion of the first neural network while offline.
    Type: Application
    Filed: May 13, 2016
    Publication date: December 8, 2016
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160358068
    Abstract: Reducing computations in a neural network may include determining a group including a plurality of convolution kernels of a convolution stage of a neural network. The convolution kernels of the group are similar to one another. A base convolution kernel for the group may be determined. Scaling factors for a plurality of input feature maps processed by the group may be calculated. The convolution stage of the neural network may be modified to calculate a composite input feature map using the scaling factors and apply the base convolution kernel to the composite input feature map.
    Type: Application
    Filed: February 3, 2016
    Publication date: December 8, 2016
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160350645
    Abstract: Executing a neural network includes generating an output tile of a first layer of the neural network by processing an input tile to the first layer and storing the output tile of the first layer in an internal memory of a processor. An output tile of a second layer of the neural network can be generated using the processor by processing the output tile of the first layer stored in the internal memory.
    Type: Application
    Filed: May 6, 2016
    Publication date: December 1, 2016
    Inventors: John W. Brothers, Joohoon Lee
  • Publication number: 20160300320
    Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 13, 2016
    Inventors: Konstantine Iourcha, John W. Brothers
  • Publication number: 20160267622
    Abstract: In a pipelined application having different stages of processing, such as a graphics application or an image processing application, there may be a dependence of one compute kernel upon another. Data associated with individual kernels needs to be written and read. A technique to minimize a need to read and write kernel data to external memory utilize at least one of fusing kernels, resizing workgroups, and performing interleaving of kernels.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Inventors: John W. BROTHERS, Santosh ABRAHAM, Joohoon LEE, Abhinav GOLAS, Seonggun KIM
  • Patent number: 9378560
    Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: June 28, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Konstantine Iourcha, John W. Brothers
  • Publication number: 20150379684
    Abstract: A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 31, 2015
    Inventors: Karthik RAMANI, Abhinav GOLAS, John W. BROTHERS
  • Publication number: 20150379671
    Abstract: A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.
    Type: Application
    Filed: March 11, 2015
    Publication date: December 31, 2015
    Inventors: John W. BROTHERS, Santosh ABRAHAM
  • Publication number: 20150379682
    Abstract: Processing vertex attribute data may include selecting a plurality of vertices of vertex attribute data and forming groups of components of the plurality of vertices according to component type. Packets of an encoded type or a generic type may be formed on a per group basis according to a data type of the components of each respective group.
    Type: Application
    Filed: May 18, 2015
    Publication date: December 31, 2015
    Inventors: Abhinav Golas, Karthik W. Ramani, John W. Brothers
  • Publication number: 20150379734
    Abstract: Graphics processing is performed in which a decision is made in individual tiles whether or not to sample at a reduced sampling rate. A sampling pattern is selected from a set of sampling patterns having the same reduced sampling rate. The sampling pattern is dithered over a set of frames to reduce the visual appearance of visual artifacts via temporal color averaging.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 31, 2015
    Inventors: Abhinav GOLAS, Karthik RAMANI, John W. BROTHERS
  • Publication number: 20150379674
    Abstract: In a graphics processing system pixel data and vertex coordinate information from a previous frame is buffered and provided to the current frame. A decision is made in the current frame whether pixel data from the previous frame may be reused. In one implementation if the speed of pixels in a tile is less than a quasi-static speed threshold a decision is made whether or not to reuse a fraction of pixels from the previous frame.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 31, 2015
    Inventors: Abhinav GOLAS, Karthik RAMANI, John W. BROTHERS
  • Publication number: 20150379692
    Abstract: A graphics system includes a reconstruction unit that utilizes higher order polynomials, such as cubic splines, to reconstruct missing pixel data. The computational work to perform interpolation with higher order polynomials, such as cubic splines, is reduced by pre-calculating weights for each sparse sample pattern. The pre-calculated weights may be stored as stencils and used during runtime to perform interpolation.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 31, 2015
    Inventors: Abhinav GOLAS, Karthik RAMANI, John W. BROTHERS
  • Publication number: 20150379727
    Abstract: An apparatus, system and method is provided to determine a motion of pixels in local regions of a scene, classify the motion into a speed category, and make decisions on how to render blocks of pixels. In one implementation the motion in a tile is classified into at least three different speed regimes. If the pixels in a tile are in a quasi-static speed regime, a determination is made whether or not to reuse a fraction of pixels from the previous frame. If the pixels are determined to be in a high speed regime, a decision is made whether or not a sampling rate may be reduced.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 31, 2015
    Inventors: Abhinav GOLAS, Karthik RAMANI, Christopher T. CHENG, John W. BROTHERS, Liangjun ZHANG, Santosh ABRAHAM, Ki Fung CHOW