Patents by Inventor John W. Faistl

John W. Faistl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10678712
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Publication number: 20190188158
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: Robert S. Chappell, John W. FAISTL, Hermann W. GARTLER, Michael D. TUCKNOTT, Rajesh S. PARTHASARATHY, David W. Burns
  • Patent number: 10216650
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Publication number: 20180225228
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 9, 2018
    Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
  • Patent number: 9880948
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
  • Publication number: 20170097902
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
  • Patent number: 9524263
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns
  • Publication number: 20140006661
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns