Patents by Inventor John W. Golz
John W. Golz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162192Abstract: A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.Type: ApplicationFiled: November 15, 2022Publication date: May 16, 2024Inventors: Arvind Kumar, Todd Edward Takken, John W Golz, Joshua M. Rubin
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Publication number: 20240103065Abstract: A semiconductor integrated circuit device includes: an active bridge; a first chiplet and a second chiplet mounted onto the active bridge; and a short-to-long converter circuit (SLCC) that has analog and digital portions. The active bridge includes at least the analog portion of the SLCC, which is electrically connected to at least the first chiplet; and a short-reach physical layer that electrically connects the first chiplet and the second chiplet. The first chiplet includes a first logic core; a first chiplet interface that is electrically connected between the first logic core and the SLCC; and a second chiplet interface that is electrically connected between the first logic core and the second chiplet. The second chiplet includes a second logic core; and a third chiplet interface that is electrically connected between the second logic core and the second chiplet interface. The active bridge also can include a built-in-self-test (BIST) circuit.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Arvind Kumar, Ramachandra Divakaruni, Mukta Ghate Farooq, John W. Golz, JIN PING HAN, Mounir Meghelli
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Publication number: 20230326854Abstract: Embodiments of present invention provide a semiconductor chip. The semiconductor chip includes a device layer having a first and a second circuit region; a frontside distribution network (FSDN) above the device layer and powering the first circuit region; and a backside distribution network (BSDN) below the device layer and powering the second circuit region, wherein the BSDN is electrically connected to the FSDN through the device layer and the FSDN is electrically connected to the first circuit region through one or more frontside metal layers, and wherein the BSDN is electrically connected to transistors of the second circuit region through the device layer.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Inventors: Albert M. Chu, Brent A. Anderson, Junli Wang, John W. Golz, Nicholas Anthony Lanzillo, Lawrence A. Clevenger
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Patent number: 9870979Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.Type: GrantFiled: August 24, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
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Patent number: 9559040Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.Type: GrantFiled: December 30, 2013Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
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Patent number: 9543229Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: December 27, 2013Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Patent number: 9536809Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: August 30, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150371927Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: ApplicationFiled: August 30, 2015Publication date: December 24, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, JR., Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150364401Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
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Publication number: 20150187642Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Mark Jacunski, Toshiaki Kirihata
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Publication number: 20150187733Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Patent number: 7046572Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: GrantFiled: June 16, 2003Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventors: David R. Hansen, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
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Patent number: 7023758Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: GrantFiled: August 17, 2005Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: David R. Hanson, Gregory J Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
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Patent number: 6845033Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.Type: GrantFiled: March 5, 2003Date of Patent: January 18, 2005Assignee: International Business Machines CorporationInventors: Toshiaki Kirihata, John W. Golz
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Publication number: 20040252573Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: International Business Machine CorporationInventors: David R. Hanson, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
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Publication number: 20040240246Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Inventors: John W. Golz, David R. Hanson, Hoki Kim
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Patent number: 6816397Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.Type: GrantFiled: May 29, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: John W. Golz, David R. Hanson, Hoki Kim
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Publication number: 20040174733Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.Type: ApplicationFiled: March 5, 2003Publication date: September 9, 2004Applicant: International Business Machines CorporationInventors: Toshiaki Kirihata, John W Golz
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Patent number: 6768143Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.Type: GrantFiled: August 26, 2003Date of Patent: July 27, 2004Assignee: International Business Machines CorporationInventors: Gregory J. Fredeman, John W. Golz, David R. Hanson, Hoki Kim
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Patent number: 6747890Abstract: Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size.Type: GrantFiled: April 2, 2003Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Toshiaki Kirihata, Subramanian S. Iyer, John W. Golz